[PATCH 2/2] PCI: dw-rockchip: hide broken ATS capability

[Niklas Cassel]

Hello Shawn,

On Tue, Feb 25, 2025 at 09:35:22AM +0800, Shawn Lin wrote:
> On 2025/2/22 4:26, Niklas Cassel wrote:
> > When running the rk3588 in endpoint mode, with an Intel host with IOMMU
> > enabled, the host side prints:
> > DMAR: VT-d detected Invalidation Time-out Error: SID 0
> > 
> > When running the rk3588 in endpoint mode, with an AMD host with IOMMU
> > enabled, the host side prints:
> > iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0]
> > 
> > Usually, to handle these issues, we add a quirk for the PCI vendor and
> > device ID in drivers/pci/quirks.c with quirk_no_ats(). That is because
> > we cannot usually modify the capabilities on the EP side.
> > 
> > In this case, we can modify the capabilties on the EP side. Thus, hide the
> > broken ATS capability on rk3588 when running in EP mode. That way,
> 
> Niklas, Thanks for reporting this issue. It's been a while before
> getting confirmation from the design team. Now I can confirm the ATS support
> for RK3588 is only available running as RC but I'm still
> requesting erratum about this issue if possible.
> 
> Acked-by: Shawn Lin <shawn.lin at rock-chips.com>

Thank you for confirming!

Considering that rock5b running in RC mode:
# lspci -vvvs 0000:00:00.0 | grep Capa
        Capabilities: [40] Power Management version 3
        Capabilities: [50] MSI: Enable+ Count=16/32 Maskable+ 64bit+
        Capabilities: [70] Express (v2) Root Port (Slot-), IntMsgNum 8
        Capabilities: [b0] MSI-X: Enable- Count=128 Masked-
        Capabilities: [100 v2] Advanced Error Reporting
        Capabilities: [148 v1] Secondary PCI Express
        Capabilities: [190 v1] L1 PM Substates
        Capabilities: [1d0 v1] Vendor Specific Information: ID=0002 Rev=4 Len=100 <?>
        Capabilities: [2d0 v1] Vendor Specific Information: ID=0006 Rev=0 Len=018 <?>

and rock5b running in EP mode:
# lspci -vvvs 0000:01:00.0 | grep Capa
        Capabilities: [40] Power Management version 3
        Capabilities: [50] MSI: Enable+ Count=32/32 Maskable+ 64bit+
        Capabilities: [70] Express (v2) Endpoint, IntMsgNum 8
        Capabilities: [b0] MSI-X: Enable- Count=2048 Masked-
        Capabilities: [100 v2] Advanced Error Reporting
        Capabilities: [148 v1] Secondary PCI Express
        Capabilities: [178 v1] Page Request Interface (PRI)
                Page Request Capacity: 00000001, Page Request Allocation: 00000000
        Capabilities: [188 v1] Latency Tolerance Reporting
        Capabilities: [190 v1] L1 PM Substates
        Capabilities: [1a0 v1] Dynamic Power Allocation <?>
        Capabilities: [1d0 v1] Vendor Specific Information: ID=0002 Rev=4 Len=100 <?>
        Capabilities: [2d0 v1] Vendor Specific Information: ID=0006 Rev=0 Len=018 <?>
        Capabilities: [2e8 v1] Physical Resizable BAR

already exposes different Capabilities (depending on the mode the PCIe
controller is running in), I would say that it slightly confusing that
Synopsys chose not to hide the ATS Capability when the PCIe controller
is running in EP mode.
So, I would guess that there is an errata for this.

But I think that your confirmation is enough.
Will take a while before I can send out a V2 though, but quite confident
that we can get something merged in time for 6.15.


Kind regards,
Niklas