[PATCH v1 2/2] arm64: dts: rockchip: add DTs for 100ASK DShanPi A1
Andrew Lunn
andrew at lunn.ch
Thu Aug 21 06:24:11 PDT 2025
> +&gmac0 {
> + phy-mode = "rgmii-id";
> + clock_in_out = "output";
> + phy-handle = <&rgmii_phy0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <ð0m0_miim
> + ð0m0_tx_bus2
> + ð0m0_rx_bus2
> + ð0m0_rgmii_clk
> + ð0m0_rgmii_bus>;
> + status = "okay";
> +};
> +
> +&gmac1 {
> + phy-mode = "rgmii-id";
> + clock_in_out = "output";
> + phy-handle = <&rgmii_phy1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <ð1m0_miim
> + ð1m0_tx_bus2
> + ð1m0_rx_bus2
> + ð1m0_rgmii_clk
> + ð1m0_rgmii_bus
> + ðm0_clk1_25m_out>;
> + status = "okay";
> +};
> +&mdio0 {
> + rgmii_phy0: phy at 1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
> + clocks = <&cru REFCLKO25M_GMAC0_OUT>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac0_rst>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&mdio1 {
> + rgmii_phy1: phy at 1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
> + clocks = <&cru REFCLKO25M_GMAC1_OUT>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1_rst>;
> + reset-assert-us = <20000>;
> + reset-deassert-us = <100000>;
> + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
> + };
> +};
For these nodes only:
Reviewed-by: Andrew Lunn <andrew at lunn.ch>
Andrew
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