[PATCH v4 1/3] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()
Manivannan Sadhasivam
manivannan.sadhasivam at linaro.org
Sun Apr 27 04:25:39 PDT 2025
On Thu, 17 Apr 2025 08:35:09 +0800, Shawn Lin wrote:
> Two mistakes here:
> 1. 0x11 is L0 not L0S, so the naming is wrong from the very beginning.
> 2. It's totally broken if enabling ASPM as rockchip_pcie_link_up() treat
> other states, for instance, L0S or L1 as link down which is obviously
> wrong.
>
> Remove the check.
>
> [...]
Applied, thanks!
[1/3] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()
commit: 7d9b5d6115532cf90a789ed6afd3f4c70ebbd827
[2/3] PCI: dw-rockchip: Enable L0S capability
commit: 198e69cc4150aba1e7af740a2111ace6a267779e
[3/3] PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to .init()
(no commit info)
Best regards,
--
Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
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