[PATCH] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

[Cristian Ciocaltea]

Hi Algea,

On 4/25/25 5:37 AM, Algea Cao wrote:
> When using HDMI PLL frequency division coefficient at 50.25MHz
> that calculated by rk_hdptx_phy_clk_pll_calc(), it is failed to

s/that/that is/
s/is failed/it fails/

> get PHY LANE lock. Although the calculated values are within the
> allowable range of PHY PLL configuration.
> 
> So we manually calculated PHY PLL frequency division coefficient
> at 50.25Mhz and added it to ropll_tmds_cfg. Manually calculated
> value  can make PHY LANE lock normally and output 50.25MHz normally.

I'd reword this paragraph using imperative sentences, e.g.:

In order to fix the PHY LANE lock error and provide the expected
50.25MHz output, manually compute the required PHY PLL frequency
division coefficient and add it to ropll_tmds_cfg configuration table.

> Signed-off-by: Algea Cao <algea.cao at rock-chips.com>
> ---
>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index fe7c05748356..77236f012a1f 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -476,6 +476,8 @@ static const struct ropll_config ropll_tmds_cfg[] = {
>  	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
>  	{ 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
>  	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
> +	{ 502500, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
> +	  4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
>  	{ 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
>  	  1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
>  	{ 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,

With the above fixed,

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>

Thanks,
Cristian