[PATCH] arm64: dts: rockchip: Move L3 cache under CPUs in RK356x SoC dtsi

[Robin Murphy]

On 2024-09-26 8:49 am, Dragan Simic wrote:
> Move the "l3_cache" node under the "cpus" node in the dtsi file for Rockchip
> RK356x SoCs.  There's no need for this cache node to be at the higher level.

Except it does arguably represent the physical topology - the L3 cache 
doesn't belong to the CPUs, it belongs to the DSU, which very much is 
"outside" the CPUs.

Thanks,
Robin.

> 
> Fixes: 8612169a05c5 ("arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x")
> Cc: stable at vger.kernel.org
> Signed-off-by: Dragan Simic <dsimic at manjaro.org>
> ---
>   arch/arm64/boot/dts/rockchip/rk356x.dtsi | 24 ++++++++++++------------
>   1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 4690be841a1c..9f7136e5d553 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -113,19 +113,19 @@ cpu3: cpu at 300 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l3_cache>;
>   		};
> -	};
>   
> -	/*
> -	 * There are no private per-core L2 caches, but only the
> -	 * L3 cache that appears to the CPU cores as L2 caches
> -	 */
> -	l3_cache: l3-cache {
> -		compatible = "cache";
> -		cache-level = <2>;
> -		cache-unified;
> -		cache-size = <0x80000>;
> -		cache-line-size = <64>;
> -		cache-sets = <512>;
> +		/*
> +		 * There are no private per-core L2 caches, but only the
> +		 * L3 cache that appears to the CPU cores as L2 caches
> +		 */
> +		l3_cache: l3-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
>   	};
>   
>   	cpu0_opp_table: opp-table-0 {
> 
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