[PATCH v3 10/12] gpio: rockchip: support new version gpio
Ye Zhang
ye.zhang at rock-chips.com
Tue Sep 3 00:36:47 PDT 2024
The next version gpio controller on SoCs like rk3576 which support four
OS operation and four interrupts
Signed-off-by: Ye Zhang <ye.zhang at rock-chips.com>
---
drivers/gpio/gpio-rockchip.c | 29 ++++++++++++++++++++---------
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 579701ad3c6f..6deebf1dd9dd 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -36,6 +36,7 @@
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
#define GPIO_TYPE_V2 (0x01000C2B)
#define GPIO_TYPE_V2_1 (0x0101157C)
+#define GPIO_TYPE_V2_2 (0x010219C8)
static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
@@ -85,7 +86,7 @@ static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
{
void __iomem *reg = bank->reg_base + offset;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
gpio_writel_v2(value, reg);
else
writel(value, reg);
@@ -97,7 +98,7 @@ static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 value;
- if (bank->gpio_type == GPIO_TYPE_V2)
+ if (bank->gpio_type >= GPIO_TYPE_V2)
value = gpio_readl_v2(reg);
else
value = readl(reg);
@@ -112,7 +113,7 @@ static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
if (value)
data = BIT(bit % 16) | BIT(bit % 16 + 16);
else
@@ -133,7 +134,7 @@ static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
void __iomem *reg = bank->reg_base + offset;
u32 data;
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
data = readl(bit >= 16 ? reg + 0x4 : reg);
data >>= bit % 16;
} else {
@@ -220,12 +221,18 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
if (!freq)
return -EINVAL;
div = (u64)(GENMASK(23, 0) + 1) * HZ_PER_MHZ;
- max_debounce = DIV_ROUND_CLOSEST_ULL(div, freq);
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, freq);
+ else
+ max_debounce = DIV_ROUND_CLOSEST_ULL(div, 2 * freq);
if (debounce > max_debounce)
return -EINVAL;
div = (u64)debounce * freq;
- div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1;
+ if (bank->gpio_type == GPIO_TYPE_V2)
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC) - 1;
+ else
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC / 2) - 1;
}
raw_spin_lock_irqsave(&bank->slock, flags);
@@ -411,7 +418,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
if (type == IRQ_TYPE_EDGE_BOTH) {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
bank->gpio_regs->int_bothedge);
goto out;
@@ -430,7 +437,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity |= mask;
}
} else {
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
bank->gpio_regs->int_bothedge);
} else {
@@ -536,7 +543,7 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
}
gc = irq_get_domain_generic_chip(bank->domain, 0);
- if (bank->gpio_type == GPIO_TYPE_V2) {
+ if (bank->gpio_type >= GPIO_TYPE_V2) {
gc->reg_writel = gpio_writel_v2;
gc->reg_readl = gpio_readl_v2;
}
@@ -669,6 +676,10 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_type = GPIO_TYPE_V2;
break;
+ case GPIO_TYPE_V2_2:
+ bank->gpio_regs = &gpio_regs_v2;
+ bank->gpio_type = GPIO_TYPE_V2_2;
+ break;
default:
dev_err(bank->dev, "cannot get the version ID\n");
return -ENODEV;
--
2.34.1
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