[PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function

[kernel test robot]

Hi Anand,

kernel test robot noticed the following build errors:

[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com
patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function
config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406200818.CQ7DXNSZ-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/pci/controller/pcie-rockchip-ep.c:20:
>> drivers/pci/controller/pcie-rockchip.h:311:31: error: array type has incomplete element type 'struct clk_bulk_data'
     311 |         struct  clk_bulk_data clks[ROCKCHIP_NUM_CLKS];
         |                               ^~~~


vim +311 drivers/pci/controller/pcie-rockchip.h

   298	
   299	struct rockchip_pcie {
   300		void	__iomem *reg_base;		/* DT axi-base */
   301		void	__iomem *apb_base;		/* DT apb-base */
   302		bool    legacy_phy;
   303		struct  phy *phys[MAX_LANE_NUM];
   304		struct	reset_control *core_rst;
   305		struct	reset_control *mgmt_rst;
   306		struct	reset_control *mgmt_sticky_rst;
   307		struct	reset_control *pipe_rst;
   308		struct	reset_control *pm_rst;
   309		struct	reset_control *aclk_rst;
   310		struct	reset_control *pclk_rst;
 > 311		struct  clk_bulk_data clks[ROCKCHIP_NUM_CLKS];
   312		struct	regulator *vpcie12v; /* 12V power supply */
   313		struct	regulator *vpcie3v3; /* 3.3V power supply */
   314		struct	regulator *vpcie1v8; /* 1.8V power supply */
   315		struct	regulator *vpcie0v9; /* 0.9V power supply */
   316		struct	gpio_desc *ep_gpio;
   317		u32	lanes;
   318		u8      lanes_map;
   319		int	link_gen;
   320		struct	device *dev;
   321		struct	irq_domain *irq_domain;
   322		int     offset;
   323		void    __iomem *msg_region;
   324		phys_addr_t msg_bus_addr;
   325		bool is_rc;
   326		struct resource *mem_res;
   327	};
   328	

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