[PATCH v6 5/6] arm64: dts: rockchip: Add VEPU121 to RK3588

[Nicolas Dufresne]

Le jeudi 13 juin 2024 à 15:48 +0200, Sebastian Reichel a écrit :
> From: Emmanuel Gil Peyrot <linkmauve at linkmauve.fr>
> 
> RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
               Hantro H1

H1 is the encoder core, G1 is the decoder core, and this exists as a combo on
this platform (vpu121).

> but can be used as a cluster (i.e. sharing work between the cores).
> These cores are called VEPU121 in the TRM. The TRM describes one more
> VEPU121, but that is combined with a Hantro H1. That one will be handled
> using the VPU binding instead.
> 
> Signed-off-by: Emmanuel Gil Peyrot <linkmauve at linkmauve.fr>
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>

Acked-by: Nicolas Dufresne <nicolas.dufresne at collabora.com>

> ---
>  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 6ac5ac8b48ab..dd85d4e55922 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -1159,6 +1159,86 @@ power-domain at RK3588_PD_SDMMC {
>  		};
>  	};
>  
> +	vepu121_0: video-codec at fdba0000 {
> +		compatible = "rockchip,rk3588-vepu121";
> +		reg = <0x0 0xfdba0000 0x0 0x800>;
> +		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vepu121_0_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	vepu121_0_mmu: iommu at fdba0800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba0800 0x0 0x40>;
> +		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	vepu121_1: video-codec at fdba4000 {
> +		compatible = "rockchip,rk3588-vepu121";
> +		reg = <0x0 0xfdba4000 0x0 0x800>;
> +		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vepu121_1_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	vepu121_1_mmu: iommu at fdba4800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba4800 0x0 0x40>;
> +		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	vepu121_2: video-codec at fdba8000 {
> +		compatible = "rockchip,rk3588-vepu121";
> +		reg = <0x0 0xfdba8000 0x0 0x800>;
> +		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vepu121_2_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	vepu121_2_mmu: iommu at fdba8800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba8800 0x0 0x40>;
> +		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	vepu121_3: video-codec at fdbac000 {
> +		compatible = "rockchip,rk3588-vepu121";
> +		reg = <0x0 0xfdbac000 0x0 0x800>;
> +		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&vepu121_3_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	vepu121_3_mmu: iommu at fdbac800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdbac800 0x0 0x40>;
> +		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
>  	av1d: video-codec at fdc70000 {
>  		compatible = "rockchip,rk3588-av1-vpu";
>  		reg = <0x0 0xfdc70000 0x0 0x800>;