[PATCH v4 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
Manivannan Sadhasivam
mani at kernel.org
Wed Jun 5 00:35:06 PDT 2024
On Wed, May 29, 2024 at 10:28:58AM +0200, Niklas Cassel wrote:
> Refactor the rockchip-dw-pcie binding to move generic properties to a new
> rockchip-dw-pcie-common binding that can be shared by both RC and EP mode.
>
> No functional change intended.
>
> Signed-off-by: Niklas Cassel <cassel at kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
- Mani
> Reviewed-by: Rob Herring (Arm) <robh at kernel.org>
> ---
> .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++
> .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +----------------
> 2 files changed, 114 insertions(+), 90 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
> new file mode 100644
> index 000000000000..60d190a77580
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
> +
> +maintainers:
> + - Shawn Lin <shawn.lin at rock-chips.com>
> + - Simon Xue <xxm at rock-chips.com>
> + - Heiko Stuebner <heiko at sntech.de>
> +
> +description: |+
> + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
> + SoCs.
> +
> +properties:
> + clocks:
> + minItems: 5
> + items:
> + - description: AHB clock for PCIe master
> + - description: AHB clock for PCIe slave
> + - description: AHB clock for PCIe dbi
> + - description: APB clock for PCIe
> + - description: Auxiliary clock for PCIe
> + - description: PIPE clock
> + - description: Reference clock for PCIe
> +
> + clock-names:
> + minItems: 5
> + items:
> + - const: aclk_mst
> + - const: aclk_slv
> + - const: aclk_dbi
> + - const: pclk
> + - const: aux
> + - const: pipe
> + - const: ref
> +
> + interrupts:
> + items:
> + - description:
> + Combined system interrupt, which is used to signal the following
> + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
> + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
> + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
> + - description:
> + Combined PM interrupt, which is used to signal the following
> + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
> + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
> + linkst_out_l0s, pm_dstate_update
> + - description:
> + Combined message interrupt, which is used to signal the following
> + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
> + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
> + - description:
> + Combined legacy interrupt, which is used to signal the following
> + interrupts - inta, intb, intc, intd
> + - description:
> + Combined error interrupt, which is used to signal the following
> + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
> + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
> + nf_err_rx, f_err_rx, radm_qoverflow
> +
> + interrupt-names:
> + items:
> + - const: sys
> + - const: pmc
> + - const: msg
> + - const: legacy
> + - const: err
> +
> + num-lanes: true
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: pcie-phy
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + minItems: 1
> + maxItems: 2
> +
> + reset-names:
> + oneOf:
> + - const: pipe
> + - items:
> + - const: pwr
> + - const: pipe
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - num-lanes
> + - phys
> + - phy-names
> + - power-domains
> + - resets
> + - reset-names
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> index 5f719218c472..550d8a684af3 100644
> --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> @@ -4,7 +4,7 @@
> $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: DesignWare based PCIe controller on Rockchip SoCs
> +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
>
> maintainers:
> - Shawn Lin <shawn.lin at rock-chips.com>
> @@ -12,12 +12,13 @@ maintainers:
> - Heiko Stuebner <heiko at sntech.de>
>
> description: |+
> - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
> + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
> PCIe IP and thus inherits all the common properties defined in
> snps,dw-pcie.yaml.
>
> allOf:
> - $ref: /schemas/pci/snps,dw-pcie.yaml#
> + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
>
> properties:
> compatible:
> @@ -40,61 +41,6 @@ properties:
> - const: apb
> - const: config
>
> - clocks:
> - minItems: 5
> - items:
> - - description: AHB clock for PCIe master
> - - description: AHB clock for PCIe slave
> - - description: AHB clock for PCIe dbi
> - - description: APB clock for PCIe
> - - description: Auxiliary clock for PCIe
> - - description: PIPE clock
> - - description: Reference clock for PCIe
> -
> - clock-names:
> - minItems: 5
> - items:
> - - const: aclk_mst
> - - const: aclk_slv
> - - const: aclk_dbi
> - - const: pclk
> - - const: aux
> - - const: pipe
> - - const: ref
> -
> - interrupts:
> - items:
> - - description:
> - Combined system interrupt, which is used to signal the following
> - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
> - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
> - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
> - - description:
> - Combined PM interrupt, which is used to signal the following
> - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
> - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
> - linkst_out_l0s, pm_dstate_update
> - - description:
> - Combined message interrupt, which is used to signal the following
> - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
> - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
> - - description:
> - Combined legacy interrupt, which is used to signal the following
> - interrupts - inta, intb, intc, intd
> - - description:
> - Combined error interrupt, which is used to signal the following
> - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
> - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
> - nf_err_rx, f_err_rx, radm_qoverflow
> -
> - interrupt-names:
> - items:
> - - const: sys
> - - const: pmc
> - - const: msg
> - - const: legacy
> - - const: err
> -
> legacy-interrupt-controller:
> description: Interrupt controller node for handling legacy PCI interrupts.
> type: object
> @@ -119,47 +65,14 @@ properties:
>
> msi-map: true
>
> - num-lanes: true
> -
> - phys:
> - maxItems: 1
> -
> - phy-names:
> - const: pcie-phy
> -
> - power-domains:
> - maxItems: 1
> -
> ranges:
> minItems: 2
> maxItems: 3
>
> - resets:
> - minItems: 1
> - maxItems: 2
> -
> - reset-names:
> - oneOf:
> - - const: pipe
> - - items:
> - - const: pwr
> - - const: pipe
> -
> vpcie3v3-supply: true
>
> required:
> - - compatible
> - - reg
> - - reg-names
> - - clocks
> - - clock-names
> - msi-map
> - - num-lanes
> - - phys
> - - phy-names
> - - power-domains
> - - resets
> - - reset-names
>
> unevaluatedProperties: false
>
>
> --
> 2.45.1
>
--
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