[PATCH v2 3/7] dts: arm64: rockchip: Add rk3576 pcie nodes

[Kever Yang]

Hi Krzysztof,

On 2024/12/22 14:38, Krzysztof Kozlowski wrote:
> On Fri, Dec 20, 2024 at 06:15:47PM +0800, Kever Yang wrote:
>> rk3576 has two pcie controller, both are pcie2x1 used with
>> naneng-combphy.
>>
>> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
>> ---
> Please use subject prefixes matching the subsystem. You can get them for
> example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>
Will update with arm64: dts: .
>> Changes in v2:
>> - Update clock and reset names and sequence to pass DTB check
>>
>>   arch/arm64/boot/dts/rockchip/rk3576.dtsi | 109 +++++++++++++++++++++++
>>   1 file changed, 109 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>> index a147879da501..df7dfe702221 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>> @@ -1016,6 +1016,115 @@ qos_npu_m1ro: qos at 27f22100 {
>>   			reg = <0x0 0x27f22100 0x0 0x20>;
>>   		};
>>   
>> +		pcie0: pcie at 2a200000 {
>> +			compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
>> +			bus-range = <0x0 0xf>;
> Follow DTS coding style in properties order and everything around here.

I can do it for most of the properties, but is there any other rules 
other than sort,

eg. compatible and reg in the beginning and status in the end?


Thanks,

- Kever

>
> Best regards,
> Krzysztof
>
>