[PATCH v4 07/21] PM / devfreq: rockchip-dfi: introduce channel mask

[Sascha Hauer]

On Tue, May 16, 2023 at 04:50:09PM +0100, Jonathan Cameron wrote:
> On Fri,  5 May 2023 13:38:42 +0200
> Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> > Different Rockchip SoC variants have a different number of channels.
> > Introduce a channel mask to make the number of channels configurable
> > from SoC initialization code.
> 
> If it's just numbers, why not a count rather than a mask?

It's a mask in the downstream driver. I guess it's not necessarily the
first channels that are enabled when not all channels are enabled. It
could also be channels 0 and 2 that are enabled.

I don't have any example board for this case though, so I can only
guess.

> > -	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> > -		u32 a = count.c[i].access - last->c[i].access;
> > -		u32 t = count.c[i].total - last->c[i].total;
> > +	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
> > +		u32 a, t;
> > +
> > +		if (!(dfi->channel_mask & BIT(i)))
> > +			continue;
> > +
> > +		a = count.c[i].access - last->c[i].access;
> > +		t = count.c[i].total - last->c[i].total;
> >  
> >  		if (a > access) {
> >  			access = a;
> > @@ -186,6 +194,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> >  	dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> >  			RK3399_PMUGRF_DDRTYPE_MASK;
> >  
> > +	dfi->channel_mask = 3;
> 
> GENMASK(1, 0)

OK.

Sascha

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