[PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz

[Heiko Stuebner]

On Wed, 14 Jun 2023 16:47:50 +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
      commit: 17c6d0c5f2a4dd3f48e300d77c93780d5c36a37e

Best regards,
-- 
Heiko Stuebner <heiko at sntech.de>