[PATCH v3 1/2] irqchip/gic-v3: Add Rockchip 3588001 errata workaround

[Marc Zyngier]

On Mon, 17 Apr 2023 22:40:34 +0100,
Sebastian Reichel <sebastian.reichel at collabora.com> wrote:
> 
> Rockchip RK3588/RK3588s GIC600 integration does not support the
> sharability feature. Rockchip assigned Errata ID #3588001 for this
> issue.

s/Errata/Erratum/ (here and in the subject).

> 
> Note, that the 0x0201743b ID is not Rockchip specific and thus
> there is an extra of_machine_is_compatible() check.
> 
> The flag are named BROKEN_SHAREABILITY to be vendor agnostic,

Either "the flag is" or "the flags are".

> since apparently similar integration design errors exist in other
> platforms and they can reuse the same flag.
> 
> Co-developed-by: XiaoDong Huang <derrick.huang at rock-chips.com>
> Signed-off-by: XiaoDong Huang <derrick.huang at rock-chips.com>
> Co-developed-by: Kever Yang <kever.yang at rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> Co-developed-by: Lucas Tanure <lucas.tanure at collabora.com>
> Signed-off-by: Lucas Tanure <lucas.tanure at collabora.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
> ---
>  Documentation/arm64/silicon-errata.rst |  3 +++
>  arch/arm64/Kconfig                     | 10 ++++++++
>  drivers/irqchip/irq-gic-v3-its.c       | 35 ++++++++++++++++++++++++++
>  3 files changed, 48 insertions(+)
> 
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index ec5f889d7681..46d06ed3e4f4 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -205,6 +205,9 @@ stable kernels.
>  +----------------+-----------------+-----------------+-----------------------------+
>  | Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |
>  +----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Rockchip       | RK3588          | #3588001        | ROCKCHIP_ERRATUM_3588001    |
> ++----------------+-----------------+-----------------+-----------------------------+
>  
>  +----------------+-----------------+-----------------+-----------------------------+
>  | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 1023e896d46b..1bc43faef10a 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1150,6 +1150,16 @@ config NVIDIA_CARMEL_CNP_ERRATUM
>  
>  	  If unsure, say Y.
>  
> +config ROCKCHIP_ERRATUM_3588001
> +	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
> +	default y
> +	help
> +	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
> +	  This means, that the GIC600 may not use the GIC600 sharability feature

This sentence makes little sense. It is the GIC driver that cannot
make use of the shareability attributes.

> +	  even though it is supported by the IP itself.
> +
> +	  If unsure, say Y.
> +
>  config SOCIONEXT_SYNQUACER_PREITS
>  	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
>  	default y
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 586271b8aa39..5b7aa48dde25 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -42,9 +42,11 @@
>  #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
>  #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
>  #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
> +#define ITS_FLAGS_BROKEN_SHAREABILITY		(1ULL << 3)

Having slept on it, I'd rather this is renamed as
"FORCE_NON_SHAREABLE", as it better describes what we are doing. The
brokenness is an attribute of the platform, not of the flag.

>
>  #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
>  #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
> +#define RDIST_FLAGS_BROKEN_SHAREABILITY		(1 << 2)

Same thing here.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.