[PATCH] pinctrl/rockchip: re-fix RK3308 pinmux bits

[Jianqun Xu]

Part of pins from RK3308 SoCs have two registers to do pinmux, one is
the origin register with 2bits named by gpioxx_sel, and another with
3bits and named by gpioxx_sel_plus.

The default value is 2bits. But Rockchip downstream pinctrl driver has a
soc init for RK3308 to switch to the 3bits path. The first patch
upstream the support for RK3308 pinctrl but drop the soc init codes.

The commit 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") try
to fix back to 2 bits path, but that will makes some iomux not be
supported.

This patch re-fix the pinmux bits to 3bits path.

Fixes: 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits")

Signed-off-by: Jianqun Xu <jay.xu at rock-chips.com>
---
 drivers/pinctrl/pinctrl-rockchip.c | 84 ++++++++++++++++++++++++------
 1 file changed, 67 insertions(+), 17 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 32e41395fc76..293077450d10 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -535,35 +535,35 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 		.bit = 8,
 		.mask = 0xf
 	}, {
-		/* gpio2a2_sel */
+		/* gpio2a2_sel_plus */
 		.num = 2,
 		.pin = 2,
-		.reg = 0x40,
-		.bit = 4,
-		.mask = 0x3
+		.reg = 0x608,
+		.bit = 0,
+		.mask = 0x7
 	}, {
-		/* gpio2a3_sel */
+		/* gpio2a3_sel_plus */
 		.num = 2,
 		.pin = 3,
-		.reg = 0x40,
-		.bit = 6,
-		.mask = 0x3
+		.reg = 0x608,
+		.bit = 4,
+		.mask = 0x7
 	}, {
-		/* gpio2c0_sel */
+		/* gpio2c0_sel_plus */
 		.num = 2,
 		.pin = 16,
-		.reg = 0x50,
-		.bit = 0,
-		.mask = 0x3
+		.reg = 0x610,
+		.bit = 8,
+		.mask = 0x7
 	}, {
-		/* gpio3b2_sel */
+		/* gpio3b2_sel_plus */
 		.num = 3,
 		.pin = 10,
-		.reg = 0x68,
-		.bit = 4,
-		.mask = 0x3
+		.reg = 0x610,
+		.bit = 0,
+		.mask = 0x7
 	}, {
-		/* gpio3b3_sel */
+		/* gpio3b3_sel_plus */
 		.num = 3,
 		.pin = 11,
 		.reg = 0x68,
@@ -3014,6 +3014,50 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
 			 rockchip_pinctrl_resume);
 
+
+static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
+{
+	int ret;
+
+	#define RK3308_GRF_SOC_CON13	(0x608)
+	#define RK3308_GRF_SOC_CON15	(0x610)
+
+	/* RK3308_GRF_SOC_CON13 */
+	#define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL	(BIT(16 + 10) | BIT(10))
+	#define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL	(BIT(16 + 7)  | BIT(7))
+	#define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL	(BIT(16 + 3)  | BIT(3))
+
+	/* RK3308_GRF_SOC_CON15 */
+	#define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL	(BIT(16 + 11) | BIT(11))
+	#define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL	(BIT(16 + 7)  | BIT(7))
+	#define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL	(BIT(16 + 3)  | BIT(3))
+
+	/*
+	 * Enable the special ctrl of selected sources.
+	 *
+	 * Example reference to GRF_SOC_CON13 description:
+	 *
+	 * gpio2a2_sel_src_ctrl
+	 * IOMUX control source selection.
+	 * 1'b0: use basic GPIO2A_IOMUX[gpio2a2_sel]
+	 * 1'b1: use gpio2a2_sel_plus instead of GPIO2A_IOMUX[gpio2a2_sel]
+	 */
+
+	ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
+			   RK3308_GRF_I2C3_IOFUNC_SRC_CTRL |
+			   RK3308_GRF_GPIO2A3_SEL_SRC_CTRL |
+			   RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
+	if (ret)
+		return ret;
+
+	ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
+			   RK3308_GRF_GPIO2C0_SEL_SRC_CTRL |
+			   RK3308_GRF_GPIO3B3_SEL_SRC_CTRL |
+			   RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
+
+	return ret;
+}
+
 static int rockchip_pinctrl_probe(struct platform_device *pdev)
 {
 	struct rockchip_pinctrl *info;
@@ -3079,6 +3123,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 			return PTR_ERR(info->regmap_pmu);
 	}
 
+	if (ctrl->type == RK3308) {
+		ret = rk3308_soc_data_init(info);
+		if (ret)
+			return ret;
+	}
+
 	ret = rockchip_pinctrl_register(pdev, info);
 	if (ret)
 		return ret;
-- 
2.25.1