[PATCHv1 06/19] clk: rockchip: Add clock controller for the RK3588

[kernel test robot]

Hi Sebastian,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linusw-pinctrl/devel linus/master v5.18-rc4 next-20220429]
[cannot apply to rockchip/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Sebastian-Reichel/Basic-RK3588-Support/20220423-013425
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20220430/202204300329.BL2rwfwr-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/6736e6f1e32bb98780b77b5aa64fe5ac5dfaae26
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Sebastian-Reichel/Basic-RK3588-Support/20220423-013425
        git checkout 6736e6f1e32bb98780b77b5aa64fe5ac5dfaae26
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/rockchip/ drivers/media/platform/qcom/venus/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

   drivers/clk/rockchip/clk-rk3588.c: In function 'rk3588_clk_init':
>> drivers/clk/rockchip/clk-rk3588.c:2408:22: warning: variable 'clks' set but not used [-Wunused-but-set-variable]
    2408 |         struct clk **clks;
         |                      ^~~~


vim +/clks +2408 drivers/clk/rockchip/clk-rk3588.c

  2403	
  2404	static void __init rk3588_clk_init(struct device_node *np)
  2405	{
  2406		struct rockchip_clk_provider *ctx;
  2407		void __iomem *reg_base;
> 2408		struct clk **clks;
  2409	
  2410		reg_base = of_iomap(np, 0);
  2411		if (!reg_base) {
  2412			pr_err("%s: could not map cru region\n", __func__);
  2413			return;
  2414		}
  2415	
  2416		ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
  2417		if (IS_ERR(ctx)) {
  2418			pr_err("%s: rockchip clk init failed\n", __func__);
  2419			iounmap(reg_base);
  2420			return;
  2421		}
  2422		clks = ctx->clk_data.clks;
  2423	
  2424		rockchip_clk_register_plls(ctx, rk3588_pll_clks,
  2425					   ARRAY_SIZE(rk3588_pll_clks),
  2426					   RK3588_GRF_SOC_STATUS0);
  2427	
  2428		rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
  2429				mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
  2430				&rk3588_cpulclk_data, rk3588_cpulclk_rates,
  2431				ARRAY_SIZE(rk3588_cpulclk_rates));
  2432		rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
  2433				mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p),
  2434				&rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
  2435				ARRAY_SIZE(rk3588_cpub0clk_rates));
  2436		rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
  2437				mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p),
  2438				&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
  2439				ARRAY_SIZE(rk3588_cpub1clk_rates));
  2440	
  2441		rockchip_clk_register_branches(ctx, rk3588_clk_branches,
  2442					       ARRAY_SIZE(rk3588_clk_branches));
  2443	
  2444		rockchip_register_softrst(np, 49158, reg_base + RK3588_SOFTRST_CON(0),
  2445					  ROCKCHIP_SOFTRST_HIWORD_MASK);
  2446	
  2447		rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
  2448	
  2449		rockchip_clk_of_add_provider(np, ctx);
  2450	}
  2451	

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