[PATCH v2] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values

[Sebastian Fricke]

Hey Benjamin,

On 26.04.2022 15:50, Benjamin Gaignard wrote:
>Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2
>register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT
>flag value.
>This fix CAINIT_G_SHARP_3 test in fluster.

just a small typo:
s/fix/fixes the/

Greetings,
Sebastian
>
>Signed-off-by: Benjamin Gaignard <benjamin.gaignard at collabora.com>
>---
> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>index 6deb31b7b993..503f4b028bc5 100644
>--- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>@@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx)
> 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
> 	}
>
>-	if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
>-		hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>-		hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>-	} else {
>-		hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
>-		hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
>-	}
>+	hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
>+	hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
>
> 	hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
> 	hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
>-- 
>2.32.0
>