[PATCH v2 3/3] drm/rockchip: dsi: Disable PLL clock on bind error

Brian Norris briannorris at chromium.org
Tue Sep 28 14:11:10 PDT 2021

On Mon, Sep 27, 2021 at 9:16 PM Chen-Yu Tsai <wenst at chromium.org> wrote:
> On Tue, Sep 28, 2021 at 2:00 AM Brian Norris <briannorris at chromium.org> wrote:
> >
> > Fix some error handling here noticed in review of other changes.
> >
> > Reported-by: Chen-Yu Tsai <wenst at chromium.org>
> > Signed-off-by: Brian Norris <briannorris at chromium.org>
> Fixes: 2d4f7bdafd70 ("drm/rockchip: dsi: migrate to use dw-mipi-dsi
> bridge driver")
> Otherwise,
> Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>

I'll add these tags, thanks.

> Additionally, I would move patch 2 and this patch before the first patch,
> as these two fix a commit introduced in v5.0, while the first patch fixes
> something introduced in v5.14. This would make automatic backporting cleaner.

Personally, I prioritize putting user-visible fixes first, and more
cosmetic things (like error handling that we ~never hit) later. Also,
the buggy commit was already backported to all still-supported stable
releases where it was relevant (i.e., 5.4+), so if these get
backported, they all should.


[1] 43c2de1002d2 drm/rockchip: dsi: move all lane config except LCDC
mux to bind()

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