[PATCH v3 0/4] Fix Rockchip MIPI DSI display init timeouts

[Heiko Stuebner]

On Tue, 28 Sep 2021 14:35:48 -0700, Brian Norris wrote:
> The Rockchip DSI driver has had a number of bugs over time and has
> usually only worked by chance. A number of users have noticed that
> things regressed with commit 43c2de1002d2 ("drm/rockchip: dsi: move all
> lane config except LCDC mux to bind()"), although it was fixing several
> real issues of its own that had been present forever in the upstream
> driver (but notably, not in the downstream/BSP driver).
> 
> [...]

Applied, thanks!

[1/4] drm/rockchip: dsi: Hold pm-runtime across bind/unbind
      commit: 514db871922f103886ad4d221cf406b4fcc5e74a
[2/4] drm/rockchip: dsi: Reconfigure hardware on resume()
      commit: e584cdc1549932f87a2707b56bc588cfac5d89e0
[3/4] drm/rockchip: dsi: Fix unbalanced clock on probe error
      commit: 251888398753924059f3bb247a44153a2853137f
[4/4] drm/rockchip: dsi: Disable PLL clock on bind error
      commit: 5a614570172e1c9f59035d259dd735acd4f1c01b

Best regards,
-- 
Heiko Stuebner <heiko at sntech.de>