[PATCH 4/9] i2c: cadence: Simplify with dev_err_probe()

Michal Simek monstr at monstr.eu
Wed Jun 23 01:59:50 PDT 2021


st 2. 9. 2020 v 17:10 odesílatel Krzysztof Kozlowski <krzk at kernel.org> napsal:
>
> Common pattern of handling deferred probe can be simplified with
> dev_err_probe().  Less code and the error value gets printed.
>
> Signed-off-by: Krzysztof Kozlowski <krzk at kernel.org>
> ---
>  drivers/i2c/busses/i2c-cadence.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
> index e4b7f2a951ad..eefde554c50c 100644
> --- a/drivers/i2c/busses/i2c-cadence.c
> +++ b/drivers/i2c/busses/i2c-cadence.c
> @@ -1214,11 +1214,10 @@ static int cdns_i2c_probe(struct platform_device *pdev)
>                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
>
>         id->clk = devm_clk_get(&pdev->dev, NULL);
> -       if (IS_ERR(id->clk)) {
> -               if (PTR_ERR(id->clk) != -EPROBE_DEFER)
> -                       dev_err(&pdev->dev, "input clock not found.\n");
> -               return PTR_ERR(id->clk);
> -       }
> +       if (IS_ERR(id->clk))
> +               return dev_err_probe(&pdev->dev, PTR_ERR(id->clk),
> +                                    "input clock not found.\n");
> +
>         ret = clk_prepare_enable(id->clk);
>         if (ret)
>                 dev_err(&pdev->dev, "Unable to enable clock.\n");
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Also this one is pending but still possible to apply without any conflict.

Acked-by: Michal Simek <michal.simek at xilinx.com>

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs



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