[PATCH] clk: rk3308: make ddrphy4x clock critical

[Heiko Stuebner]

On Wed, 21 Jul 2021 20:48:16 +0800, Yunhao Tian wrote:
> Currently, no driver support for DDR memory controller (DMC) is present,
> as a result, no driver is explicitly consuming the ddrphy clock. This means
> that VPLL1 (parent of ddr clock) will be shutdown if we enable
> and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX).
> If VPLL1 is disabled, the whole system will freeze, because the DDR
> controller will lose its clock. So, it's necessary to prevent VPLL1 from
> shutting down, by marking the ddrphy4x CLK_IS_CRITICAL.
> 
> [...]

Applied, thanks!

[1/1] clk: rk3308: make ddrphy4x clock critical
      commit: c0c81245dac7caaef4db627fb7043495d1afe662

Though I moved the clock to the pre-existing
list of critical clocks.

I'm still hoping for that handoff mechanism before
we sprinkle CLK_IS_CRITICAL throughout the clock trees.


Best regards,
-- 
Heiko Stuebner <heiko at sntech.de>