[PATCH 4/9] arm64: dts: rockchip: add rk356x gmac1 node

[Peter Geis]

On Wed, Jul 28, 2021 at 10:21 AM Heiko Stübner <heiko at sntech.de> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:29 CEST schrieb Peter Geis:
> > Add the gmac1 controller to the rk356x device tree.
> > This is the controller common to both the rk3568 and rk3566.
> >
> > Signed-off-by: Peter Geis <pgwipeout at gmail.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 48 ++++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index c2aa7aeec58d..77c679304916 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -18,6 +18,7 @@ / {
> >       #size-cells = <2>;
> >
> >       aliases {
> > +             ethernet1 = &gmac1;
> >               gpio0 = &gpio0;
> >               gpio1 = &gpio1;
> >               gpio2 = &gpio2;
>
> Looking back at the discussion about mmc aliases in board-dts vs. soc-dtsi
> I get the feeling the ethernet alias would be same case, as not all boards
> will expose ethernet.
>
> In the very least the ethernet alias should be part of the rk3566/rk3568 dtsi
> files, doing ethernet0 = &gmac1 for rk3566 and ethernet1 = &gmac1 for rk3568.
>
> But I do think the board-dts would be the more appropriate place.

Okay, that makes sense, I'll move this to the board.
In regards to the 0 vs 1, this was to avoid issues with downstream
u-boot/rkbin which treats the rk3566 as a rk3568.
Currently it doesn't seem to affect anything in the way the kernel
probes it, as it still shows up as eth0.

>
>
> Heiko
>
> > @@ -344,6 +345,53 @@ sdmmc2: mmc at fe000000 {
> >               status = "disabled";
> >       };
> >
> > +     gmac1: ethernet at fe010000 {
> > +             compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
> > +             reg = <0x0 0xfe010000 0x0 0x10000>;
> > +             interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > +             interrupt-names = "macirq", "eth_wake_irq";
> > +             clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
> > +                      <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
> > +                      <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
> > +                      <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
> > +             clock-names = "stmmaceth", "mac_clk_rx",
> > +                           "mac_clk_tx", "clk_mac_refout",
> > +                           "aclk_mac", "pclk_mac",
> > +                           "clk_mac_speed", "ptp_ref";
> > +             resets = <&cru SRST_A_GMAC1>;
> > +             reset-names = "stmmaceth";
> > +             rockchip,grf = <&grf>;
> > +             snps,mixed-burst;
> > +             snps,tso;
> > +             snps,axi-config = <&gmac1_stmmac_axi_setup>;
> > +             snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
> > +             snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
> > +             status = "disabled";
> > +
> > +             mdio1: mdio {
> > +                     compatible = "snps,dwmac-mdio";
> > +                     #address-cells = <0x1>;
> > +                     #size-cells = <0x0>;
> > +             };
> > +
> > +             gmac1_stmmac_axi_setup: stmmac-axi-config {
> > +                     snps,wr_osr_lmt = <4>;
> > +                     snps,rd_osr_lmt = <8>;
> > +                     snps,blen = <0 0 0 0 16 8 4>;
> > +             };
> > +
> > +             gmac1_mtl_rx_setup: rx-queues-config {
> > +                     snps,rx-queues-to-use = <1>;
> > +                     queue0 {};
> > +             };
> > +
> > +             gmac1_mtl_tx_setup: tx-queues-config {
> > +                     snps,tx-queues-to-use = <1>;
> > +                     queue0 {};
> > +             };
> > +     };
> > +
> >       qos_gpu: qos at fe128000 {
> >               compatible = "rockchip,rk3568-qos", "syscon";
> >               reg = <0x0 0xfe128000 0x0 0x20>;
> >
>
>
>
>