回复: [PATCH] clk: rk3308: make ddrphy4x clock critical

[Tian Yunhao]

Quoting Stephen Boyd <sboyd at kernel.org>

> Is it not enabled by default?

Indeed it's enabled by default upon power-up, but it's not
called by any clk_enable (if you look at clk_summary, enable
count is 0). The clk framework thinks that it's an unnecessary
clock, and decides the parent, VPLL1, can be shutdown any time.

If you enable and then disable its siblings (like mclk_i2s0_8ch_in),
 the clk framework will think that VPLL1 is no longer necessary, 
thus shutdown this PLL. This will cause DDR to lose clock.