[PATCH v1 1/5] dt-bindings: usb: convert rockchip, dwc3.txt to yaml
Rob Herring
robh+dt at kernel.org
Tue Feb 2 15:06:42 EST 2021
On Mon, Feb 1, 2021 at 2:46 PM Johan Jonker <jbx6244 at gmail.com> wrote:
>
> Hi Rob,
>
> See questions below.
>
> Kind regards,
>
> Johan Jonker
>
> On 2/1/21 8:41 PM, Johan Jonker wrote:
> > In the past Rockchip dwc3 usb nodes were manually checked.
> > With the conversion of snps,dwc3.yaml as common document
> > we now can convert rockchip,dwc3.txt to yaml as well.
> >
> > Added properties for rk3399 are:
> > resets
> > reset-names
> >
> > Generic properties that are now also filtered:
> > "#address-cells"
> > "#size-cells"
> > ranges
> >
> > Signed-off-by: Johan Jonker <jbx6244 at gmail.com>
> > ---
> > .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 -----------
> > .../devicetree/bindings/usb/rockchip,dwc3.yaml | 107 +++++++++++++++++++++
> > 2 files changed, 107 insertions(+), 56 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > deleted file mode 100644
> > index 945204932..000000000
> > --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> > +++ /dev/null
> > @@ -1,56 +0,0 @@
> > -Rockchip SuperSpeed DWC3 USB SoC controller
> > -
> > -Required properties:
> > -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
> > -- clocks: A list of phandle + clock-specifier pairs for the
> > - clocks listed in clock-names
> > -- clock-names: Should contain the following:
> > - "ref_clk" Controller reference clk, have to be 24 MHz
> > - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
> > - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
> > - operation and >= 30MHz for HS operation
> > - "grf_clk" Controller grf clk
> > -
> > -Required child node:
> > -A child node must exist to represent the core DWC3 IP block. The name of
> > -the node is not important. The content of the node is defined in dwc3.txt.
> > -
> > -Phy documentation is provided in the following places:
> > -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
> > -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
> > -
> > -Example device nodes:
> > -
> > - usbdrd3_0: usb at fe800000 {
> > - compatible = "rockchip,rk3399-dwc3";
> > - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> > - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> > - clock-names = "ref_clk", "suspend_clk",
> > - "bus_clk", "grf_clk";
> > - #address-cells = <2>;
> > - #size-cells = <2>;
> > - ranges;
> > - usbdrd_dwc3_0: dwc3 at fe800000 {
> > - compatible = "snps,dwc3";
> > - reg = <0x0 0xfe800000 0x0 0x100000>;
> > - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > - dr_mode = "otg";
> > - };
> > - };
> > -
> > - usbdrd3_1: usb at fe900000 {
> > - compatible = "rockchip,rk3399-dwc3";
> > - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> > - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> > - clock-names = "ref_clk", "suspend_clk",
> > - "bus_clk", "grf_clk";
> > - #address-cells = <2>;
> > - #size-cells = <2>;
> > - ranges;
> > - usbdrd_dwc3_1: dwc3 at fe900000 {
> > - compatible = "snps,dwc3";
> > - reg = <0x0 0xfe900000 0x0 0x100000>;
> > - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> > - dr_mode = "otg";
> > - };
> > - };
> > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > new file mode 100644
> > index 000000000..681086fa6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > @@ -0,0 +1,107 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip SuperSpeed DWC3 USB SoC controller
> > +
> > +maintainers:
> > + - Heiko Stuebner <heiko at sntech.de>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - rockchip,rk3399-dwc3
> > +
> > + clocks:
> > + items:
> > + - description:
> > + Controller reference clock, must to be 24 MHz
> > + - description:
> > + Controller suspend clock, must to be 24 MHz or 32 KHz
> > + - description:
> > + Master/Core clock, must to be >= 62.5 MHz for SS
> > + operation and >= 30MHz for HS operation
> > + - description:
> > + Controller aclk_usb3_rksoc_axi_perf clock
> > + - description:
> > + Controller aclk_usb3 clock
> > + - description:
> > + Controller grf clock
> > +
> > + clock-names:
> > + items:
> > + - const: ref_clk
> > + - const: suspend_clk
> > + - const: bus_clk
>
> > + - const: aclk_usb3_rksoc_axi_perf
> > + - const: aclk_usb3
>
> This was not in the original document, but is needed to compile.
Okay, fine to add it. That's common.
> > + - const: grf_clk
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + const: usb3-otg
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + ranges: true
> > +
> > +patternProperties:
> > + "^usb@[a-f0-9]+$":
> > + type: object
> > +
> > + $ref: "snps,dwc3.yaml"
> > +
> > + description:
> > + A child node must exist to represent the core DWC3 IP block.
> > + The content of the node is defined in snps,dwc3.yaml.
> > +
> > + Phy documentation is provided in the following places.
> > +
> > + USB2.0 PHY
> > + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> > +
> > + Type-C PHY
> > + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> > +
> > + unevaluatedProperties: false
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - "#address-cells"
> > + - "#size-cells"
> > + - ranges
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/rk3399-cru.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> > + usbdrd3_0: usb at fe800000 {
>
> The rk3399 has 2 dwc3 usb nodes. When we remove @fe800000 and @fe900000
> in the rk3399.dtsi it complains about 2 identical usb root nodenames.
> For this example to pass change to:
>
> usbdrd3_0: usb ??
>
> What to do with it in the dtsi??
The correct thing is really that there shouldn't have been 2 nodes in
the first place. I think the first DWC3 user had some wrapper
registers where separate nodes kind of make sense. But just for
clocks, not really needed.
> > + compatible = "rockchip,rk3399-dwc3";
> > + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> > + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
> > + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
> > + clock-names = "ref_clk", "suspend_clk",
> > + "bus_clk", "aclk_usb3_rksoc_axi_perf",
> > + "aclk_usb3", "grf_clk";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> > + ranges;
>
> Ranges generates notifications. Could you advise if that is needed in
> this dwc3 usb context and rk3399.dtsi or should it be removed?
A non-empty ranges will solve all your problems:
ranges = <0 0xfe800000 0 0xfe800000 0 0x100000>;
>
> > + usbdrd_dwc3_0: usb at fe800000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0xfe800000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "otg";
> > + };
> > + };
> >
>
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