[PATCH 6/7] rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
Kever Yang
kever.yang at rock-chips.com
Sat Aug 8 05:58:25 EDT 2020
在 2020/7/24 下午6:51, Jagan Teki 写道:
> PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
>
> C.TOUCH 2.0 10.1" Open Frame is a Carrier board with Capacitive
> touch 10.1" open frame from Engicam.
>
> PX30.Core needs to mount on top of this Carrier board for creating
> complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
> Note:
> - Linux ML link:
> https://lkml.org/lkml/2020/7/23/523
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/px30-px30-core-ctouch2-of10.dts | 21 ++++
> arch/arm/mach-rockchip/px30/Kconfig | 7 ++
> board/rockchip/evb_px30/MAINTAINERS | 6 +
> configs/px30-core-ctouch2-of10-px30_defconfig | 108 ++++++++++++++++++
> 5 files changed, 143 insertions(+)
> create mode 100644 arch/arm/dts/px30-px30-core-ctouch2-of10.dts
> create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8198808ba5..270de39823 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
> dtb-$(CONFIG_ROCKCHIP_PX30) += \
> px30-evb.dtb \
> px30-firefly.dtb \
> + px30-px30-core-ctouch2-of10.dtb \
> px30-px30-core-edimm2.2.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RK3036) += \
> diff --git a/arch/arm/dts/px30-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-px30-core-ctouch2-of10.dts
> new file mode 100644
> index 0000000000..9c957a21e3
> --- /dev/null
> +++ b/arch/arm/dts/px30-px30-core-ctouch2-of10.dts
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (c) 2020 Engicam srl
> + * Copyright (c) 2020 Amarula Solutions(India)
> + */
> +
> +/dts-v1/;
> +#include "px30.dtsi"
> +#include "px30-engicam-ctouch2-of10.dtsi"
> +#include "px30-px30-core.dtsi"
> +
> +/ {
> + model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
> + compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-px30-core",
> + "rockchip,px30";
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +};
> diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
> index f1fa225251..21e7bbcd7f 100644
> --- a/arch/arm/mach-rockchip/px30/Kconfig
> +++ b/arch/arm/mach-rockchip/px30/Kconfig
> @@ -14,6 +14,13 @@ config TARGET_EVB_PX30
> * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
> PX30.Core EDIMM2.2 Starter Kit.
>
> + PX30.Core CTOUCH2 OF10:
> + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
> + * CTOUCH2 OF 10 is a Carrier board with Capacitive touch 10.1"
> + Open frame from Engicam.
> + * PX30.Core needs to mount on top of CTOUCH2 OF10 for creating complete
> + PX30.Core C.TOUCH 2.0 10.1\" Open Frame.
> +
> config ROCKCHIP_BOOT_MODE_REG
> default 0xff010200
>
> diff --git a/board/rockchip/evb_px30/MAINTAINERS b/board/rockchip/evb_px30/MAINTAINERS
> index 48fba4e046..459626e679 100644
> --- a/board/rockchip/evb_px30/MAINTAINERS
> +++ b/board/rockchip/evb_px30/MAINTAINERS
> @@ -11,3 +11,9 @@ M: Jagan Teki <jagan at amarulasolutions.com>
> M: Suniel Mahesh <sunil at amarulasolutions.com>
> S: Maintained
> F: configs/px30-core-edimm2.2-px30_defconfig
> +
> +PX30-Core-CTOUCH2-OF10
> +M: Jagan Teki <jagan at amarulasolutions.com>
> +M: Suniel Mahesh <sunil at amarulasolutions.com>
> +S: Maintained
> +F: configs/px30-core-ctouch2-of10-px30_defconfig
> diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
> new file mode 100644
> index 0000000000..b87b61f740
> --- /dev/null
> +++ b/configs/px30-core-ctouch2-of10-px30_defconfig
> @@ -0,0 +1,108 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00200000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SPL_TEXT_BASE=0x00000000
> +CONFIG_ROCKCHIP_PX30=y
> +CONFIG_TARGET_EVB_PX30=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_DEBUG_UART_BASE=0xFF160000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_CONSOLE_MUX is not set
> +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2-of10.dtb"
> +CONFIG_MISC_INIT_R=y
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_STACK_R=y
> +# CONFIG_TPL_BANNER_PRINT is not set
> +CONFIG_SPL_CRC32_SUPPORT=y
> +CONFIG_SPL_ATF=y
> +# CONFIG_TPL_FRAMEWORK is not set
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_LZMADEC is not set
> +# CONFIG_CMD_UNZIP is not set
> +CONFIG_CMD_GPT=y
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +# CONFIG_CMD_ITEST is not set
> +# CONFIG_CMD_SETEXPR is not set
> +# CONFIG_CMD_MISC is not set
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2-of10"
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x800800
> +CONFIG_FASTBOOT_BUF_SIZE=0x04000000
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
> +CONFIG_ROCKCHIP_OTP=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_ROCKCHIP_SDRAM_COMMON=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_RNG=y
> +CONFIG_RNG_ROCKCHIP=y
> +# CONFIG_SPECIFY_CONSOLE_INDEX is not set
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_DEBUG_UART_SKIP_INIT=y
> +CONFIG_SOUND=y
> +CONFIG_SYSRESET=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_DISPLAY=y
> +CONFIG_LCD=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
> +CONFIG_LZO=y
> +CONFIG_ERRNO_STR=y
> +# CONFIG_EFI_LOADER is not set
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