[PATCH 2/3] clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228

Heiko Stuebner heiko at sntech.de
Fri Mar 23 00:51:40 PDT 2018

Am Mittwoch, 21. März 2018, 03:39:19 CET schrieb Shawn Lin:
> commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
> if clock rate is zero") catches one gremlin again for clk-rk3228.c
> that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
> sclk_sdmmc. However, I don't like the name of sclk_sdmmc0, so I now
> rename it to be sclk_sdmmc.
> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>

applied to my clk-branch after adapting the commit message a bit,
so that it is less about personal taste and highlights the discrepancy
in the manual between clk_sdmmc0 and hclk_sdmmc (without 0)
and we thus standardize on the one without 0.


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