[PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO

Heiko Stuebner heiko at sntech.de
Mon Mar 12 03:52:54 PDT 2018

Am Montag, 12. März 2018, 02:50:48 CET schrieb Shunqian Zheng:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
> Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>

applied for 4.17


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