[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

[Heiko Stübner]

Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
> 
> Signed-off-by: Daniel Schultz <d.schultz at phytec.de>

applied for 4.17


Thanks
Heiko