[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

Heiko Stübner heiko at sntech.de
Mon Mar 5 12:25:30 PST 2018

Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
> Signed-off-by: Daniel Schultz <d.schultz at phytec.de>

applied for 4.17


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