[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing
heiko at sntech.de
Mon Mar 5 06:15:46 PST 2018
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
> Signed-off-by: Daniel Schultz <d.schultz at phytec.de>
> The binding will be added with the next merge of net-next:
I did find the commit, but no related change of the dp83867 dt binding
document , including a review by dt-maintainers.
While your property does not look overly complicated, the binding
should be updated nontheless.
> arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
> 1 file changed, 1 insertion(+)
> diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
> index bdd80aa..e60535d 100644
> --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
> +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
> @@ -141,6 +141,7 @@
> ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
More information about the Linux-rockchip