[PATCH] ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

Heiko Stuebner heiko at sntech.de
Wed Mar 22 05:01:30 PDT 2017

Am Mittwoch, 22. März 2017, 00:14:28 CET schrieb Heiko Stuebner:
> According to [0] pointed out by Marc Zyngier in a report about a
> similar error message, PPIs 11 and 13 are edge triggered on
> Cortex-A9 socs including the rk3066 and rk3188 which currently
> mark them as level triggered.
> Until some time ago the gic did not care but commit 992345a58e0c
> ("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
> introduced a warning for that case.
> Fix the warning on these socs by describing the interrupts correctly
> and also using the binding constants for easier reading in the future.
> [0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>

applied for 4.12

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