[PATCH] PCI: rockchip: Support quirk to disable 5 GT/s (PCIe 2.x) link rate
helgaas at kernel.org
Fri Sep 23 16:55:00 PDT 2016
On Thu, Sep 22, 2016 at 10:31:18AM -0700, Brian Norris wrote:
> rk3399 supports PCIe 2.x link speeds marginally at best, and on some
> boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500
> ms waiting for training that will never happen, let's support a device
> tree quirk flag to disable generation 2 speeds entirely.
> Signed-off-by: Brian Norris <briannorris at chromium.org>
> .../devicetree/bindings/pci/rockchip-pcie.txt | 2 +
> drivers/pci/host/pcie-rockchip.c | 57 +++++++++++++---------
> 2 files changed, 37 insertions(+), 22 deletions(-)
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
> index ba67b39939c1..e769726fd093 100644
> --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
> @@ -42,6 +42,8 @@ Required properties:
> Optional Property:
> - ep-gpios: contain the entry for pre-reset gpio
> - num-lanes: number of lanes to use
> +- rockchip,disable-gen2: present if PCIe generation 2.x (i.e., 5 GT/s link
> + speeds) is not supported.
> - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
> - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
> - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
We already have st,pcie-is-gen1 and fsl,max-link-speed for similar
issues. Can you copy the naming of one of those? The
"max-link-speed" one seems a little more general.
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