[PATCH v5 3/3] usb: dwc2: Properly account for the force mode delays
stefan.wahren at i2se.com
Sun Sep 11 22:20:44 PDT 2016
> Heiko Stuebner <heiko at sntech.de> hat am 11. September 2016 um 23:19
> Hi John,
> Am Mittwoch, 7. September 2016, 19:39:43 CEST schrieb John Youn:
> > When a force mode bit is set and the IDDIG debounce filter is enabled,
> > there is a delay for the forced mode to take effect. This delay is due
> > to the IDDIG debounce filter and is variable depending on the platform's
> > PHY clock speed. To account for this delay we can poll for the expected
> > mode.
> > On a clear force mode, since we don't know what mode to poll for, delay
> > for a fixed 100 ms. This is the maximum delay based on the slowest PHY
> > clock speed.
> > Tested-by: Stefan Wahren <stefan.wahren at i2se.com>
> > Signed-off-by: John Youn <johnyoun at synopsys.com>
> > ---
> > @@ -475,12 +478,6 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
> > __func__, hsotg->dr_mode);
> > break;
> > }
> > -
> > - /*
> > - * NOTE: This is required for some rockchip soc based
> > - * platforms.
> > - */
> > - msleep(50);
> > }
> sorry for not finding the time to test your subsequent versions, but this
> acts up on my Rockchip boards, as I'm still running into errors like
> [ 4.875570] usb usb2-port1: connect-debounce failed
could you please name the relevant DTS file of the affected boards?
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