[PATCH] clk: rockchip: add 400MHz to rk3066 clock rates table

Heiko Stuebner heiko at sntech.de
Sat Nov 5 15:12:00 PDT 2016

Am Freitag, 4. November 2016, 14:10:56 CET schrieb Paweł Jarosz:
> We need this to init PLL_CPLL to 400MHz at boot.
> Signed-off-by: Paweł Jarosz <paweljarosz3691 at gmail.com>

applied to my clk branch for 4.10


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