[PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk
robh at kernel.org
Thu Jun 30 19:35:52 PDT 2016
On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsultant. But for some specific usb
> cores(e.g. rk3399 soc dwc3), the default PHYIf
> configuration value is fault, so we need to
> reconfigure it by software.
> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to
> the UTMI+ PHY interface.
> Signed-off-by: William Wu <william.wu at rock-chips.com>
> Changes in v5:
> - None
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> Changes in v3:
> - None
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> Documentation/devicetree/bindings/usb/dwc3.txt | 4 ++++
> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++
> drivers/usb/dwc3/core.h | 12 ++++++++++++
> 3 files changed, 35 insertions(+)
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1ada121..34d13a5 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,10 @@ Optional properties:
> - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
> in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
> a free-running PHY clock.
> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
This isn't really what I'd call a quirk.
> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
> + with an 8- or 16-bit interface. Value 0 select 8-bit
> + interface, value 1 select 16-bit interface.
These seem like they should be standard properties for setting the phy
type/mode. I think we already have something defined in fact.
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