[PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock

Heiko Stübner heiko at sntech.de
Mon Jun 20 11:14:52 PDT 2016

Am Montag, 20. Juni 2016, 10:56:53 schrieb Douglas Anderson:
> The "phyctrl_frqsel" is described in the Arasan datasheet [1] as "the
> frequency range of DLL operation".  Although the Rockchip variant of
> this PHY has different ranges than the reference Arasan PHY it appears
> as if the functionality is similar.  We should set this phyctrl field
> properly.
> Note: as per Rockchip engineers, apparently the "phyctrl_frqsel" is
> actually only useful in HS200 / HS400 modes even though the DLL itself
> it used for some purposes in all modes.  See the discussion in the
> earlier change in this series: ("mmc: sdhci-of-arasan: Always power the
> PHY off/on when clock changes").  In any case, it shouldn't hurt to set
> this always.
> Note that this change should allow boards to run at HS200 / HS400 speed
> modes while running at 100 MHz or 150 MHz.  In fact, running HS400 at
> 150 MHz (giving 300 MB/s) is the main motivation of this series, since
> performance is still good but signal integrity problems are less
> prevelant at 150 MHz.
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
> Signed-off-by: Douglas Anderson <dianders at chromium.org>
> Acked-by: Kishon Vijay Abraham I <kishon at ti.com>

> ---
> Changes in v3:
> - Use phy_init / phy_exit (Heiko)

Reviewed-by: Heiko Stuebner <heiko at sntech.de>

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