[PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock
dianders at chromium.org
Mon Jun 13 17:45:57 PDT 2016
On Mon, Jun 13, 2016 at 5:24 PM, Shawn Lin <shawn.lin at rock-chips.com> wrote:
>>> From the public Arasan datasheet they seem to indicate +/- 15 MHz is
>> sane. Does that sound OK? Presuming that all of your numbers
>> (50/100/150/200) are centers, that means that we could support clock
>> rates of:
>> 35 MHz - 65 MHz
>> 85 MHz - 115 MHz
>> 135 MHz - 165 MHz
>> 185 MHz - 200 MHz
>> So how about if we add a warning for things that are outside of those
>> ranges? ...except no warning for < 35 MHz since presumably we're not
>> using high speed modes when the DLL is that slow and so we're OK.
> a warning should be ok.
> If we ask 150M, but PLL only provide 175M maybe, then should we
> fallback it to 150M or promote it to 200M when setting?
I made it a warning in V2 but still picked the closest reasonable
value. See what you think. The PHY really isn't in control of this
clock, so the warning is the best it can do. Presumably someone
designing a system with this PHY in it would see the warning an
realize that they should make SDHCI run at more reasonable rates...
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