[PATCH 1/2] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a-rayeager board

[Andy Yan]

Hi Heiko:

On 2016年01月14日 20:45, Heiko Stuebner wrote:
> Hi Andy,
>
> Am Donnerstag, 14. Januar 2016, 20:34:20 schrieb Andy Yan:
>> The current vdd_arm voltage is too low, increase it will make
>> the system more stable.
>>
>> Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
>> ---
>>
>>   arch/arm/boot/dts/rk3066a-rayeager.dts | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> b/arch/arm/boot/dts/rk3066a-rayeager.dts index 0bf6876..3d4c104 100644
>> --- a/arch/arm/boot/dts/rk3066a-rayeager.dts
>> +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
>> @@ -159,6 +159,14 @@
>>
>>   &cpu0 {
>>   	cpu0-supply = <&vdd_arm>;
>> +	operating-points = <
>> +		/* kHz    uV */
>> +		1008000 1125000
>> +		816000  1125000
>> +		600000  1100000
>> +		504000  1100000
>> +		312000  1075000
>> +	>;
>>   };
>>
>>   &emac {
> Does this only apply to the rayeager-board / px2 soc or for all rk3066a/px2
> boards? I.e. the original values come from some sdk kernel and I might've
> transcribed that wrong at the time and I remember having problems trying to
> reach higher frequencies as well.
>
> So could you check what the full operating points looks like for both and if
> this can move to the rk3066a.dtsi, as both should be able to reach at least
> 1.4GHz / 1.6GHz.
>
>
> Thanks
> Heiko
>
> ______

     I have checked the sdk kernel, the opp for the sdk board is like 
bellow:

  /**
  * dvfs_cpu_logic_table: table for arm and logic dvfs
  * @frequency   : arm frequency
  * @cpu_volt    : arm voltage depend on frequency
  * @logic_volt  : logic voltage arm requests depend on frequency
  * comments     : min arm/logic voltage
  */
static struct dvfs_arm_table dvfs_cpu_logic_table[] = {
         {.frequency = 252 * 1000,       .cpu_volt = 1075 * 1000,        
.logic_volt = 1125 * 1000},//0.975V/1.000V
         {.frequency = 504 * 1000,       .cpu_volt = 1100 * 1000,        
.logic_volt = 1125 * 1000},//0.975V/1.000V
         {.frequency = 816 * 1000,       .cpu_volt = 1125 * 1000,        
.logic_volt = 1150 * 1000},//1.000V/1.025V
         {.frequency = 1008 * 1000,      .cpu_volt = 1125 * 1000,        
.logic_volt = 1150 * 1000},//1.025V/1.050V
         {.frequency = 1200 * 1000,      .cpu_volt = 1175 * 1000,        
.logic_volt = 1200 * 1000},//1.100V/1.050V
         {.frequency = 1272 * 1000,      .cpu_volt = 1225 * 1000,        
.logic_volt = 1200 * 1000},//1.150V/1.100V
         {.frequency = 1416 * 1000,      .cpu_volt = 1300 * 1000,        
.logic_volt = 1200 * 1000},//1.225V/1.100V
         {.frequency = 1512 * 1000,      .cpu_volt = 1350 * 1000,        
.logic_volt = 1250 * 1000},//1.300V/1.150V
         {.frequency = 1608 * 1000,      .cpu_volt = 1425 * 1000,        
.logic_volt = 1300 * 1000},//1.325V/1.175V
         {.frequency = CPUFREQ_TABLE_END},
};

  This table is made base on mass stress test. So is a safe opp table 
for most rk3066a base boards. But it some
  board is not so well in power supply circuit design, the may also need 
to adjust it.

  From the table we see that the logic_voltage need to increase  as the 
cpufreq increase. But it seems that the current mainline kernel does not 
support adjust the logic voltage when cpufreq change. So we can only 
scale the cpufreq to 1.4GHZ by fixed the logic_volt at 1.2V.

  If you like, I can move it to rk3066a.dtsi with the max freq at 
1008MHZ, as I haven't  test to 1.4GHZ  with the mainline kernel. Or give 
me some time to test to see if the rayeager board can run to 1.4G stable 
with the mainline .
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