[PATCH] i2c: rk3x: adjust the LOW divison based on characteristics of SCL
dianders at chromium.org
Wed Sep 24 21:36:38 PDT 2014
On Wed, Sep 24, 2014 at 6:56 PM, addy ke <addy.ke at rock-chips.com> wrote:
> In my measurement,all paramter but "Data hold time" are match the characteristics of SCL bus line.
> the measured value is 0.928us("data hold time on RK3X" ~= "the low period / 2")
> but the maximum value described in table is 0.9us
> About "Data hold time", there are described in I2C specification:
> - for CBUS compatible masters for I2C-bus deivices
> - the maximum data hold time has only be met if the device does not stretch the LOW period of the SCL signal.
> I have tested on RK3288-Pinky board, there are no error.
> But I don't known whether this paramter will affect i2c communications.
I'll have to spend more time tomorrow to really understand this, but
if changing the code to bias towards slightly longer "high" times
instead of "low" times helps fix it then that's fine with me.
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