[PATCH] clk: rockchip: add missing rk3288 npll rate table
Doug Anderson
dianders at chromium.org
Wed Sep 24 20:56:57 PDT 2014
Kever,
On Wed, Sep 24, 2014 at 6:35 PM, Kever Yang <kever.yang at rock-chips.com> wrote:
> Doug,
>
>
> On 09/25/2014 06:51 AM, Doug Anderson wrote:
>>
>> Heiko,
>>
>> On Wed, Sep 24, 2014 at 2:41 PM, Heiko Stübner <heiko at sntech.de> wrote:
>>>
>>> The npll on rk3288 is exactly the same pll type as the other 4. Yet it
>>> was missing the link to the rate table, making rate changes impossible.
>>> Change that by setting the table.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
>>> ---
>>> drivers/clk/rockchip/clk-rk3288.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/rockchip/clk-rk3288.c
>>> b/drivers/clk/rockchip/clk-rk3288.c
>>> index 8ea885b..938d30b 100644
>>> --- a/drivers/clk/rockchip/clk-rk3288.c
>>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>>> @@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[]
>>> __initdata = {
>>> [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0,
>>> RK3288_PLL_CON(12),
>>> RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
>>> [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0,
>>> RK3288_PLL_CON(16),
>>> - RK3288_MODE_CON, 14, 9, NULL),
>>> + RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
>>> };
>>
>> Works for me. Any reason not to add it to dpll, too?
>
> dpll is used for DDR controller only, I'm not sure memory scaling driver
> will use
> the clock module API, because the code for memory scaling must moved to
> intmem
> (dram is not available at that time), which need to be small enough, and
> it's not
> possible to use the API from clock module.
>
> So, I think it is no need to add the rate table to dpll.
Sure. It seems to me like it wouldn't hurt to have it listed, but
you're right that it's probably impossible that it would ever be used
so I won't push for it.
Reviewed-by: Doug Anderson <dianders at chromium.org>
Tested-by: Doug Anderson <dianders at chromium.org>
-Doug
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