<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Tue, Apr 7, 2026 at 7:27 AM Inochi Amaoto <<a href="mailto:inochiama@gmail.com">inochiama@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Previous the CPU unit address cpu of sg2044 use decimal, it is<br>
not following the general convention for unit addresses of the<br>
OF. Convent the unit address to hex to resolve this problem.<br>
<br>
The introduces a small ABI break for the CPU id, but it should<br>
affect nothing since there is no direct full-path reference to<br>
these CPU nodes.<br>
<br>
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")<br>
Signed-off-by: Inochi Amaoto <<a href="mailto:inochiama@gmail.com" target="_blank">inochiama@gmail.com</a>><br>
Link: <a href="https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/" rel="noreferrer" target="_blank">https://lore.kernel.org/devicetree-spec/00ddad5a-02f5-474e-af9c-11ce7716ddfc@iscas.ac.cn/</a></blockquote><div><br>Remove the Link tag, and add:<br><br>Reviewed-by: Guo Ren <<a href="mailto:guoren@kernel.org">guoren@kernel.org</a>><br> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
---<br>
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++----------<br>
1 file changed, 118 insertions(+), 118 deletions(-)<br>
<br>
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi<br>
index 3135409c2149..f66a382c95bd 100644<br>
--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi<br>
+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi<br>
@@ -14,7 +14,7 @@ cpus {<br>
<br>
cpu0: cpu@0 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <0>;<br>
+ reg = <0x0>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller {<br>
<br>
cpu1: cpu@1 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <1>;<br>
+ reg = <0x1>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller {<br>
<br>
cpu2: cpu@2 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <2>;<br>
+ reg = <0x2>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller {<br>
<br>
cpu3: cpu@3 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <3>;<br>
+ reg = <0x3>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller {<br>
<br>
cpu4: cpu@4 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <4>;<br>
+ reg = <0x4>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller {<br>
<br>
cpu5: cpu@5 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <5>;<br>
+ reg = <0x5>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller {<br>
<br>
cpu6: cpu@6 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <6>;<br>
+ reg = <0x6>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller {<br>
<br>
cpu7: cpu@7 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <7>;<br>
+ reg = <0x7>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller {<br>
<br>
cpu8: cpu@8 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <8>;<br>
+ reg = <0x8>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller {<br>
<br>
cpu9: cpu@9 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <9>;<br>
+ reg = <0x9>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu10: cpu@10 {<br>
+ cpu10: cpu@a {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <10>;<br>
+ reg = <0xa>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu11: cpu@11 {<br>
+ cpu11: cpu@b {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <11>;<br>
+ reg = <0xb>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu12: cpu@12 {<br>
+ cpu12: cpu@c {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <12>;<br>
+ reg = <0xc>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu13: cpu@13 {<br>
+ cpu13: cpu@d {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <13>;<br>
+ reg = <0xd>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu14: cpu@14 {<br>
+ cpu14: cpu@e {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <14>;<br>
+ reg = <0xe>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu15: cpu@15 {<br>
+ cpu15: cpu@f {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <15>;<br>
+ reg = <0xf>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu16: cpu@16 {<br>
+ cpu16: cpu@10 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <16>;<br>
+ reg = <0x10>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu17: cpu@17 {<br>
+ cpu17: cpu@11 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <17>;<br>
+ reg = <0x11>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu18: cpu@18 {<br>
+ cpu18: cpu@12 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <18>;<br>
+ reg = <0x12>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu19: cpu@19 {<br>
+ cpu19: cpu@13 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <19>;<br>
+ reg = <0x13>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu20: cpu@20 {<br>
+ cpu20: cpu@14 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <20>;<br>
+ reg = <0x14>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu21: cpu@21 {<br>
+ cpu21: cpu@15 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <21>;<br>
+ reg = <0x15>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu22: cpu@22 {<br>
+ cpu22: cpu@16 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <22>;<br>
+ reg = <0x16>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu23: cpu@23 {<br>
+ cpu23: cpu@17 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <23>;<br>
+ reg = <0x17>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu24: cpu@24 {<br>
+ cpu24: cpu@18 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <24>;<br>
+ reg = <0x18>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu25: cpu@25 {<br>
+ cpu25: cpu@19 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <25>;<br>
+ reg = <0x19>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu26: cpu@26 {<br>
+ cpu26: cpu@1a {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <26>;<br>
+ reg = <0x1a>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu27: cpu@27 {<br>
+ cpu27: cpu@1b {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <27>;<br>
+ reg = <0x1b>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu28: cpu@28 {<br>
+ cpu28: cpu@1c {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <28>;<br>
+ reg = <0x1c>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu29: cpu@29 {<br>
+ cpu29: cpu@1d {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <29>;<br>
+ reg = <0x1d>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu30: cpu@30 {<br>
+ cpu30: cpu@1e {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <30>;<br>
+ reg = <0x1e>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu31: cpu@31 {<br>
+ cpu31: cpu@1f {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <31>;<br>
+ reg = <0x1f>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu32: cpu@32 {<br>
+ cpu32: cpu@20 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <32>;<br>
+ reg = <0x20>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu33: cpu@33 {<br>
+ cpu33: cpu@21 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <33>;<br>
+ reg = <0x21>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu34: cpu@34 {<br>
+ cpu34: cpu@22 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <34>;<br>
+ reg = <0x22>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu35: cpu@35 {<br>
+ cpu35: cpu@23 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <35>;<br>
+ reg = <0x23>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu36: cpu@36 {<br>
+ cpu36: cpu@24 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <36>;<br>
+ reg = <0x24>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu37: cpu@37 {<br>
+ cpu37: cpu@25 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <37>;<br>
+ reg = <0x25>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu38: cpu@38 {<br>
+ cpu38: cpu@26 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <38>;<br>
+ reg = <0x26>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu39: cpu@39 {<br>
+ cpu39: cpu@27 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <39>;<br>
+ reg = <0x27>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu40: cpu@40 {<br>
+ cpu40: cpu@28 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <40>;<br>
+ reg = <0x28>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu41: cpu@41 {<br>
+ cpu41: cpu@29 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <41>;<br>
+ reg = <0x29>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu42: cpu@42 {<br>
+ cpu42: cpu@2a {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <42>;<br>
+ reg = <0x2a>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu43: cpu@43 {<br>
+ cpu43: cpu@2b {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <43>;<br>
+ reg = <0x2b>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu44: cpu@44 {<br>
+ cpu44: cpu@2c {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <44>;<br>
+ reg = <0x2c>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu45: cpu@45 {<br>
+ cpu45: cpu@2d {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <45>;<br>
+ reg = <0x2d>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu46: cpu@46 {<br>
+ cpu46: cpu@2e {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <46>;<br>
+ reg = <0x2e>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu47: cpu@47 {<br>
+ cpu47: cpu@2f {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <47>;<br>
+ reg = <0x2f>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu48: cpu@48 {<br>
+ cpu48: cpu@30 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <48>;<br>
+ reg = <0x30>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu49: cpu@49 {<br>
+ cpu49: cpu@31 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <49>;<br>
+ reg = <0x31>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu50: cpu@50 {<br>
+ cpu50: cpu@32 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <50>;<br>
+ reg = <0x32>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu51: cpu@51 {<br>
+ cpu51: cpu@33 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <51>;<br>
+ reg = <0x33>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu52: cpu@52 {<br>
+ cpu52: cpu@34 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <52>;<br>
+ reg = <0x34>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu53: cpu@53 {<br>
+ cpu53: cpu@35 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <53>;<br>
+ reg = <0x35>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu54: cpu@54 {<br>
+ cpu54: cpu@36 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <54>;<br>
+ reg = <0x36>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu55: cpu@55 {<br>
+ cpu55: cpu@37 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <55>;<br>
+ reg = <0x37>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu56: cpu@56 {<br>
+ cpu56: cpu@38 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <56>;<br>
+ reg = <0x38>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu57: cpu@57 {<br>
+ cpu57: cpu@39 {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <57>;<br>
+ reg = <0x39>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu58: cpu@58 {<br>
+ cpu58: cpu@3a {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <58>;<br>
+ reg = <0x3a>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu59: cpu@59 {<br>
+ cpu59: cpu@3b {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <59>;<br>
+ reg = <0x3b>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu60: cpu@60 {<br>
+ cpu60: cpu@3c {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <60>;<br>
+ reg = <0x3c>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu61: cpu@61 {<br>
+ cpu61: cpu@3d {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <61>;<br>
+ reg = <0x3d>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu62: cpu@62 {<br>
+ cpu62: cpu@3e {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <62>;<br>
+ reg = <0x3e>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller {<br>
};<br>
};<br>
<br>
- cpu63: cpu@63 {<br>
+ cpu63: cpu@3f {<br>
compatible = "thead,c920", "riscv";<br>
- reg = <63>;<br>
+ reg = <0x3f>;<br>
i-cache-block-size = <64>;<br>
i-cache-size = <65536>;<br>
i-cache-sets = <512>;<br>
-- <br>
2.53.0<br>
<br>
</blockquote></div><div><br clear="all"></div><div><br></div><span class="gmail_signature_prefix">-- </span><br><div dir="ltr" class="gmail_signature"><div dir="ltr">Best Regards<br> Guo Ren<br></div></div></div>