[PATCH 1/2] perf riscv: Implement rdtsc()

[Anup Patel]

On Mon, Sep 28, 2026 at 3:20 PM Chen Pei <cp0613 at linux.alibaba.com> wrote:
>
> There is no riscv implementation of rdtsc(), so perf links against the
> weak stub in util/tsc.c and every caller reads a constant 0 that is
> indistinguishable from a real counter standing still.
>
> Implement rdtsc() over the time CSR with rdtime.  The time CSR is a TSC
> equivalent on riscv: it is readable from user mode, it ticks at a
> constant frequency, and it is the same counter that riscv's
> arch_perf_update_userpage() builds the user page conversion fields from,
> so the counter and perf time share a timebase.
>
> Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>

LGTM from RISC-V perspective.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  tools/perf/arch/riscv/util/Build |  1 +
>  tools/perf/arch/riscv/util/tsc.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 tools/perf/arch/riscv/util/tsc.c
>
> diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
> index 2328fb9a30a3..52cd6a481de8 100644
> --- a/tools/perf/arch/riscv/util/Build
> +++ b/tools/perf/arch/riscv/util/Build
> @@ -1 +1,2 @@
>  perf-util-y += header.o
> +perf-util-y += tsc.o
> diff --git a/tools/perf/arch/riscv/util/tsc.c b/tools/perf/arch/riscv/util/tsc.c
> new file mode 100644
> index 000000000000..7cc4710ac38c
> --- /dev/null
> +++ b/tools/perf/arch/riscv/util/tsc.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/types.h>
> +
> +#include "../../../util/tsc.h"
> +
> +u64 rdtsc(void)
> +{
> +       u64 val;
> +
> +       /*
> +        * The time CSR ticks at a constant frequency and is the same counter
> +        * the kernel feeds into the user page conversion fields through
> +        * sched_clock(), so it is a TSC equivalent here.
> +        */
> +       asm volatile("rdtime %0" : "=r" (val));
> +
> +       return val;
> +}
> --
> 2.50.1
>
>