[PATCH v6 10/16] irqchip/riscv-imsic: Add MSI address list

[Andrew Jones]

On Fri, Sep 25, 2026 at 05:16:53PM +0200, Andrew Jones wrote:
> Upcoming RISC-V IOMMU interrupt remapping needs to map every possible
> host IMSIC target into one contiguous MSI IOVA range. MSI message
> composition then uses the target CPU's position within that range.
> 
> Build an IMSIC physical address array indexed by logical CPU.
> Require every possible CPU to have an initialized IMSIC page before
> publishing the array. This preserves physical address zero as a valid
> target and guarantees the array has num_possible_cpus() entries.
> 
> The array size and each target's index can therefore be derived
> directly, without storing duplicate count or per-CPU index metadata.
> 
> Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> Tested-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> ---
>  drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++++++++++++++++++
>  drivers/irqchip/irq-riscv-imsic-state.h |  3 +++
>  2 files changed, 35 insertions(+)
>

Regarding the Sashiko findings for this patch. The first I already
responded to on v5[1] and the second, which is new, is complaining
about the error handing in imsic_setup_state() for the new call to
imsic_init_msi_pa_list(), but the error handling follows the pattern
of all other error handling for that function. So there is nothing
to do for Sashiko here.

[1] https://lore.kernel.org/all/20260901133835.345001-1-andrew.jones@oss.qualcomm.com/

Thanks,
drew