[PATCH] RISC-V: KVM: Replace imsic switch-case macros with range checks

[Xiaofeng Yuan]

The imsic_eix_read/swap/write/set accessors use a family of macros
that expand into a switch with 128 cases covering the EIP and EIE
register windows. This mirrors the csr_read_num() idiom required where
a CSR number must be encoded as a csrr instruction immediate (e.g.
drivers/perf/riscv_pmu.c), but here the register number is merely
written to vsiselect as data, so the expansion solves no real
constraint. It costs ~90 lines of nested macros and trips ~30
checkpatch errors and warnings.

Since the generated cases form two contiguous windows, [IMSIC_EIP0,
IMSIC_EIP63] and [IMSIC_EIE0, IMSIC_EIE63], the same behavior is
expressed with a simple range check. Introduce imsic_eix_ireg_is_valid()
and use it in the four accessors, removing the macros along with the
~30 checkpatch errors and warnings they caused.

No functional change intended. Compile tested with riscv64-linux-gnu-gcc
and tested on QEMU (RISC-V virt, AIA).

Signed-off-by: Xiaofeng Yuan <yuanxiaofeng at eswincomputing.com>
---
 arch/riscv/kvm/aia_imsic.c | 124 +++++--------------------------------
 1 file changed, 15 insertions(+), 109 deletions(-)

diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c
index c1af23e79..5b6927733 100644
--- a/arch/riscv/kvm/aia_imsic.c
+++ b/arch/riscv/kvm/aia_imsic.c
@@ -67,36 +67,17 @@ struct imsic {
 	__r;					\
 })
 
-#define imsic_read_switchcase(__ireg)			\
-	case __ireg:					\
-		return imsic_vs_csr_read(__ireg);
-#define imsic_read_switchcase_2(__ireg)			\
-	imsic_read_switchcase(__ireg + 0)		\
-	imsic_read_switchcase(__ireg + 1)
-#define imsic_read_switchcase_4(__ireg)			\
-	imsic_read_switchcase_2(__ireg + 0)		\
-	imsic_read_switchcase_2(__ireg + 2)
-#define imsic_read_switchcase_8(__ireg)			\
-	imsic_read_switchcase_4(__ireg + 0)		\
-	imsic_read_switchcase_4(__ireg + 4)
-#define imsic_read_switchcase_16(__ireg)		\
-	imsic_read_switchcase_8(__ireg + 0)		\
-	imsic_read_switchcase_8(__ireg + 8)
-#define imsic_read_switchcase_32(__ireg)		\
-	imsic_read_switchcase_16(__ireg + 0)		\
-	imsic_read_switchcase_16(__ireg + 16)
-#define imsic_read_switchcase_64(__ireg)		\
-	imsic_read_switchcase_32(__ireg + 0)		\
-	imsic_read_switchcase_32(__ireg + 32)
+static bool imsic_eix_ireg_is_valid(int ireg)
+{
+	return (ireg >= IMSIC_EIP0 && ireg <= IMSIC_EIP63) ||
+	       (ireg >= IMSIC_EIE0 && ireg <= IMSIC_EIE63);
+}
 
 static unsigned long imsic_eix_read(int ireg)
 {
-	switch (ireg) {
-	imsic_read_switchcase_64(IMSIC_EIP0)
-	imsic_read_switchcase_64(IMSIC_EIE0)
-	}
-
-	return 0;
+	if (!imsic_eix_ireg_is_valid(ireg))
+		return 0;
+	return imsic_vs_csr_read(ireg);
 }
 
 #define imsic_vs_csr_swap(__c, __v)		\
@@ -107,36 +88,11 @@ static unsigned long imsic_eix_read(int ireg)
 	__r;					\
 })
 
-#define imsic_swap_switchcase(__ireg, __v)		\
-	case __ireg:					\
-		return imsic_vs_csr_swap(__ireg, __v);
-#define imsic_swap_switchcase_2(__ireg, __v)		\
-	imsic_swap_switchcase(__ireg + 0, __v)		\
-	imsic_swap_switchcase(__ireg + 1, __v)
-#define imsic_swap_switchcase_4(__ireg, __v)		\
-	imsic_swap_switchcase_2(__ireg + 0, __v)	\
-	imsic_swap_switchcase_2(__ireg + 2, __v)
-#define imsic_swap_switchcase_8(__ireg, __v)		\
-	imsic_swap_switchcase_4(__ireg + 0, __v)	\
-	imsic_swap_switchcase_4(__ireg + 4, __v)
-#define imsic_swap_switchcase_16(__ireg, __v)		\
-	imsic_swap_switchcase_8(__ireg + 0, __v)	\
-	imsic_swap_switchcase_8(__ireg + 8, __v)
-#define imsic_swap_switchcase_32(__ireg, __v)		\
-	imsic_swap_switchcase_16(__ireg + 0, __v)	\
-	imsic_swap_switchcase_16(__ireg + 16, __v)
-#define imsic_swap_switchcase_64(__ireg, __v)		\
-	imsic_swap_switchcase_32(__ireg + 0, __v)	\
-	imsic_swap_switchcase_32(__ireg + 32, __v)
-
 static unsigned long imsic_eix_swap(int ireg, unsigned long val)
 {
-	switch (ireg) {
-	imsic_swap_switchcase_64(IMSIC_EIP0, val)
-	imsic_swap_switchcase_64(IMSIC_EIE0, val)
-	}
-
-	return 0;
+	if (!imsic_eix_ireg_is_valid(ireg))
+		return 0;
+	return imsic_vs_csr_swap(ireg, val);
 }
 
 #define imsic_vs_csr_write(__c, __v)		\
@@ -145,35 +101,10 @@ do {						\
 	csr_write(CSR_VSIREG, __v);		\
 } while (0)
 
-#define imsic_write_switchcase(__ireg, __v)		\
-	case __ireg:					\
-		imsic_vs_csr_write(__ireg, __v);	\
-		break;
-#define imsic_write_switchcase_2(__ireg, __v)		\
-	imsic_write_switchcase(__ireg + 0, __v)		\
-	imsic_write_switchcase(__ireg + 1, __v)
-#define imsic_write_switchcase_4(__ireg, __v)		\
-	imsic_write_switchcase_2(__ireg + 0, __v)	\
-	imsic_write_switchcase_2(__ireg + 2, __v)
-#define imsic_write_switchcase_8(__ireg, __v)		\
-	imsic_write_switchcase_4(__ireg + 0, __v)	\
-	imsic_write_switchcase_4(__ireg + 4, __v)
-#define imsic_write_switchcase_16(__ireg, __v)		\
-	imsic_write_switchcase_8(__ireg + 0, __v)	\
-	imsic_write_switchcase_8(__ireg + 8, __v)
-#define imsic_write_switchcase_32(__ireg, __v)		\
-	imsic_write_switchcase_16(__ireg + 0, __v)	\
-	imsic_write_switchcase_16(__ireg + 16, __v)
-#define imsic_write_switchcase_64(__ireg, __v)		\
-	imsic_write_switchcase_32(__ireg + 0, __v)	\
-	imsic_write_switchcase_32(__ireg + 32, __v)
-
 static void imsic_eix_write(int ireg, unsigned long val)
 {
-	switch (ireg) {
-	imsic_write_switchcase_64(IMSIC_EIP0, val)
-	imsic_write_switchcase_64(IMSIC_EIE0, val)
-	}
+	if (imsic_eix_ireg_is_valid(ireg))
+		imsic_vs_csr_write(ireg, val);
 }
 
 #define imsic_vs_csr_set(__c, __v)		\
@@ -182,35 +113,10 @@ do {						\
 	csr_set(CSR_VSIREG, __v);		\
 } while (0)
 
-#define imsic_set_switchcase(__ireg, __v)		\
-	case __ireg:					\
-		imsic_vs_csr_set(__ireg, __v);		\
-		break;
-#define imsic_set_switchcase_2(__ireg, __v)		\
-	imsic_set_switchcase(__ireg + 0, __v)		\
-	imsic_set_switchcase(__ireg + 1, __v)
-#define imsic_set_switchcase_4(__ireg, __v)		\
-	imsic_set_switchcase_2(__ireg + 0, __v)		\
-	imsic_set_switchcase_2(__ireg + 2, __v)
-#define imsic_set_switchcase_8(__ireg, __v)		\
-	imsic_set_switchcase_4(__ireg + 0, __v)		\
-	imsic_set_switchcase_4(__ireg + 4, __v)
-#define imsic_set_switchcase_16(__ireg, __v)		\
-	imsic_set_switchcase_8(__ireg + 0, __v)		\
-	imsic_set_switchcase_8(__ireg + 8, __v)
-#define imsic_set_switchcase_32(__ireg, __v)		\
-	imsic_set_switchcase_16(__ireg + 0, __v)	\
-	imsic_set_switchcase_16(__ireg + 16, __v)
-#define imsic_set_switchcase_64(__ireg, __v)		\
-	imsic_set_switchcase_32(__ireg + 0, __v)	\
-	imsic_set_switchcase_32(__ireg + 32, __v)
-
 static void imsic_eix_set(int ireg, unsigned long val)
 {
-	switch (ireg) {
-	imsic_set_switchcase_64(IMSIC_EIP0, val)
-	imsic_set_switchcase_64(IMSIC_EIE0, val)
-	}
+	if (imsic_eix_ireg_is_valid(ireg))
+		imsic_vs_csr_set(ireg, val);
 }
 
 static unsigned long imsic_mrif_atomic_rmw(struct imsic_mrif *mrif,
-- 
2.34.1