[PATCH v5 2/3] scsi: ufs: spacemit: k3: Add UFS Host Controller driver
Aurelien Jarno
aurelien at aurel32.net
Wed Sep 16 09:26:25 PDT 2026
Hi Yixun,
On 2026-09-16 02:59, Yixun Lan wrote:
> SpacemiT K3 SoC consist of UFS (Universal Flash Storage) Host Controller
> which has features compatible with JEDEC UFS 2.2, MIPI UniPro v1.61 and
> M-PHY v3.0 standard.
>
> Tested-by: Aurelien Jarno <aurelien at aurel32.net>
> Tested-by: Anirudh Srinivasan <asrinivasan at oss.tenstorrent.com>
> Signed-off-by: Yixun Lan <dlan at kernel.org>
> ---
> drivers/ufs/host/Kconfig | 12 +
> drivers/ufs/host/Makefile | 1 +
> drivers/ufs/host/ufs-spacemit.c | 688 ++++++++++++++++++++++++++++++++++++++++
> drivers/ufs/host/ufs-spacemit.h | 79 +++++
> 4 files changed, 780 insertions(+)
>
> diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig
> index ff170c0b6da0..6146872fcecc 100644
> --- a/drivers/ufs/host/Kconfig
> +++ b/drivers/ufs/host/Kconfig
> @@ -132,6 +132,18 @@ config SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
> bool
> default y if SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO
>
> +config SCSI_UFS_SPACEMIT
> + tristate "SpacemiT UFS controller driver"
> + depends on SCSI_UFSHCD_PLATFORM && (ARCH_SPACEMIT || COMPILE_TEST)
> + help
> + This selects the SpacemiT specific additions to UFSHCD platform driver.
> + UFS host on SpacemiT needs some vendor specific configuration before
> + accessing the hardware which includes PHY configuration and vendor
> + specific registers.
> +
> + Select this if you have UFS controller on SpacemiT chipset.
> + If unsure, say N.
> +
> config SCSI_UFS_SPRD
> tristate "Unisoc specific hooks to UFS controller platform driver"
> depends on SCSI_UFSHCD_PLATFORM && (ARCH_SPRD || COMPILE_TEST)
> diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile
> index 7d8db67eb23c..a3c447b8fc21 100644
> --- a/drivers/ufs/host/Makefile
> +++ b/drivers/ufs/host/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
> obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
> obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
> obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o
> +obj-$(CONFIG_SCSI_UFS_SPACEMIT) += ufs-spacemit.o
> obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o
> obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
> obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o
> diff --git a/drivers/ufs/host/ufs-spacemit.c b/drivers/ufs/host/ufs-spacemit.c
> new file mode 100644
> index 000000000000..179e6edb2ac2
> --- /dev/null
> +++ b/drivers/ufs/host/ufs-spacemit.c
> @@ -0,0 +1,688 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <ufs/ufshcd.h>
> +#include <ufs/ufshci.h>
> +#include <ufs/ufs_quirks.h>
> +#include <ufs/unipro.h>
> +
> +#include "ufshcd-pltfrm.h"
> +#include "ufs-spacemit.h"
> +
> +/* PA Layer Gettable and settable M-PHY Specific Attributes */
> +#define PA_TXHSG1SYNCLENGTH 0x1552
> +#define PA_TXHSG1PREPARELENGTH 0x1553
> +#define PA_TXHSG2SYNCLENGTH 0x1554
> +#define PA_TXHSG2PREPARELENGTH 0x1555
> +#define PA_TXHSG3SYNCLENGTH 0x1556
> +#define PA_TXHSG3PREPARELENGTH 0x1557
> +#define PA_TXMK2EXTENSION 0x155A
> +#define PA_PEERSCRAMBLING 0x155B
> +#define PA_TXSKIP 0x155C
> +#define PA_TXSKIPPERIOD 0x155D
> +#define PA_PEER_TX_LCC_ENABLE 0x155F
> +
> +#define PA_SCRAMBLING 0x1585
> +#define PA_MK2EXTENSIONGUARDBAND 0x15AB
> +
> +/* Special TX/RX Configuration Attributes */
> +#define RX_LS_PRE_LEN_CAP 0x008D
> +#define RX_LANE_HB8_BKDOOR_ATTR 0x00F4
> +#define RX_PWRM_CLOSURE_LEN_CAP 0x008E
> +#define RX_MIN_STALL_CAP 0x0088
> +#define RX_LANE_SOF_BKDOOR_ATT 0x00F2
> +#define RX_GARBAGE_COUNT_OFFSET 0x00F2
> +
> +/* Special analog register */
> +#define ANA_EQ_CTRL_REG_ATTR 0x00CD
> +#define ANA_HSGEAR_CTRL_ATTR 0x00C1
> +
> +/*
> + * Keep UFS ACLK at a lower parent rate (409.6MHz) for stable init.
> + * This mirrors the "ufs-low-aclk-freq" change from the other environment.
> + */
> +#define UFS_ACLK_LOW_FREQ_HZ 409600000UL
You probably want to rename that to AXI, although here it's not that
important.
> +
> +/* PHY register magic values */
> +#define MPHY_PU_ALL 0x87f
> +#define MPHY_PU_WITH_HB8_RESET 0xb7f
> +#define MPHY_DEVICE_REFCLK_OE BIT(8)
> +#define MPHY_DEVICE_HW_RESET BIT(0)
> +
> +#define MPHY_PLL_LOCK_BIT BIT(31)
> +#define MPHY_PLL_LOCK_TIMEOUT_US 10000
> +
> +/* FSM states */
> +#define FSM_STATE_HIBERN8 0x1
> +#define FSM_STATE_ACTIVE 0x3
> +#define FSM_STATE_LS_BURST 0x5
> +
> +#define VENDOR_DUMP_BUF_SIZE 2048
> +#define VENDOR_MAX_OFFSET 0xE0
> +
> +/* M-PHY FSM states */
> +#define MPHY_RX_FSM_STATE 0xC1
> +#define MPHY_TX_FSM_STATE 0x41
> +
> +static int ufs_spacemit_dme_set(struct ufs_hba *hba,
> + const struct ufshcd_dme_attr_val *v, int n)
> +{
> + int ret = 0;
> + int attr_node = 0;
> +
> + for (attr_node = 0; attr_node < n; attr_node++) {
> + ret = ufshcd_dme_set(hba, v[attr_node].attr_sel,
> + v[attr_node].mib_val);
> +
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int ufs_spacemit_check_hibern8(struct ufs_hba *hba)
> +{
> + u32 tx_fsm_val_0 = 0;
> + u32 tx_fsm_val_1 = 0;
> + int retries = DIV_ROUND_UP(HBRN8_POLL_TOUT_MS * 1000, 100);
> + int err = 0;
> +
> + do {
> + err = ufshcd_dme_get(hba,
> + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
> + &tx_fsm_val_0);
> + if (err)
> + break;
> +
> + err = ufshcd_dme_get(hba,
> + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(1)),
> + &tx_fsm_val_1);
> + if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
> + tx_fsm_val_1 == TX_FSM_HIBERN8))
> + break;
> +
> + usleep_range(100, 200);
> + } while (--retries > 0);
> +
> + if (err) {
> + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
> + __func__, err);
> + } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
> + tx_fsm_val_1 != TX_FSM_HIBERN8) {
> + err = -ETIMEDOUT;
> + dev_err(hba->dev,
> + "%s: invalid TX_FSM_STATE, lane0 = %u, lane1 = %u\n",
> + __func__, tx_fsm_val_0, tx_fsm_val_1);
> + }
> +
> + return err;
> +}
> +
> +static u32 ufs_spacemit_get_sys1clk_1us(struct ufs_hba *hba)
> +{
> + struct ufs_clk_info *clki, *ufs_aclk = NULL;
> + struct list_head *head = &hba->clk_list_head;
> + unsigned long rate_hz = 0;
> +
> + if (!list_empty(head)) {
> + list_for_each_entry(clki, head, list) {
> + if (clki->name && !strcmp(clki->name, "aclk") && clki->clk) {
On the other hand, you definitely want to rename this one to "axi" to
match the device tree change. Right now the whole patchset just doesn't
work.
> + ufs_aclk = clki;
> + break;
> + }
> + }
> + }
> +
> + if (ufs_aclk && ufs_aclk->clk)
> + rate_hz = clk_get_rate(ufs_aclk->clk);
> +
> + if (!rate_hz)
> + return 0;
> +
> + return DIV_ROUND_CLOSEST(rate_hz, 1000000);
> +}
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien at aurel32.net http://aurel32.net
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