[PATCH 5/9] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>

Document the aclint mswi compatible for the MIPS P8700 and
introduce the 'riscv,hart-indexes' property,
used to address the sparse MIPS P8700 harts.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>
---
 .../thead,c900-aclint-mswi.yaml                    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
index 62fd220e126e650e3800d8eee2a749fdbbde6108..47c04943eb0c793467aaa5570776605cae0eadfd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -17,6 +17,8 @@ properties:
               - sophgo,sg2042-aclint-mswi
               - sophgo,sg2044-aclint-mswi
           - const: thead,c900-aclint-mswi
+      - items:
+          - const: gf,mips-p8700-aclint-mswi
       - items:
           - enum:
               - anlogic,dr1v90-aclint-mswi
@@ -29,6 +31,14 @@ properties:
     minItems: 1
     maxItems: 4095
 
+  riscv,hart-indexes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4095
+    description:
+      A list of hart indexes that the MSWI device uses to address each hart
+      that is mentioned in the "interrupts-extended"
+
 additionalProperties: false
 
 required:
@@ -36,6 +46,19 @@ required:
   - reg
   - interrupts-extended
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: gf,mips-p8700-aclint-mswi
+    then:
+      required:
+        - riscv,hart-indexes
+    else:
+      properties:
+        riscv,hart-indexes: false
+
 examples:
   - |
     interrupt-controller at 94000000 {
@@ -46,4 +69,15 @@ examples:
                             <&cpu4intc 3>;
       reg = <0x94000000 0x00010000>;
     };
+
+  - |
+    mswi at 16150000 {
+      compatible = "gf,mips-p8700-aclint-mswi";
+      reg = <0x16150000 0x4000>;
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
+    };
 ...

-- 
2.43.0