[PATCH v5 0/8] Add StarFive JHB100 syscon modules

[Conor Dooley]

On Fri, Aug 28, 2026 at 02:56:00AM -0700, Changhuang Liang wrote:
> StarFive JHB100 has many syscon modules, as listed below:
> - pcieep0_ecsr_syscon	(PCIe endpoint 0 externel syscon)
> - pcieep1_ecsr_syscon
> - host0_syscon		(Host0 syscon)
> - host1_syscon
> - husb0_syscon		(Host USB 0 syscon)
> - husb1_syscon
> - husbd0_syscon		(Host USB device 0 syscon)
> - husbd1_syscon
> - husbcmn_syscon	(Host USB common syscon)
> - gpu0_syscon		(GPU0 syscon)
> - gpu1_syscon
> - b2h_syscon		(BMC to Host syscon)
> - h2b_syscon		(Host to BMC syscon)
> - vout_syscon		(Video output syscon)
> - pcierp_ecsr_syscon	(PCIe root port externel syscon)
> - pcierp_syscon		(PCIe root port syscon)
> - usb_syscon
> - npu_syscon
> - per0_syscon		(Peripheral 0 syscon)
> - per1_syscon
> - per2_syscon
> - per3_syscon
> - sys0_syscon		(System 0 syscon)
> - sys1_syscon
> - sys2_syscon
> - strap_syscon
> - sfc0_filter_syscon	(SFC0 filter syscon)
> - sfc1_filter_syscon
> - sfc2_filter_syscon
> 
> Some syscon modules contain PLL, reset, and socinfo nodes
> 
> This series depends on the series:
> https://lore.kernel.org/all/20260807112923.191627-1-changhuang.liang@starfivetech.com/

I tried to apply the soc patches, but they depend on this so I can't.
Can you get someone from Starfive, ideally one of the listed clock
maintainers, to review that series?

If you look here, about half the patches are missing a review:
https://patchwork.kernel.org/project/lei-conor/list/?series=1142160

If you do that, I'll try to sort out getting a PR sent to the clock
folks for it and figuring out how these bits can go on top.

Thanks,
Conor.
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