[PATCH v2 00/10] riscv: Add device tree support for UltraRISC DP1000
Jia Wang via B4 Relay
devnull+wangjia.ultrarisc.com at kernel.org
Mon Sep 7 02:54:39 PDT 2026
Add Devicetree support for the UltraRISC DP1000 RISC-V SoC and two
DP1000-based motherboards: Shenzhen Rongda M0 and Milk-V Titan.
DP1000 integrates eight UltraRISC CP100 CPU cores. The SoC description
includes the CPU and cache topology, CLINT, PLIC, clock controller,
pinctrl, GPIO, four UARTs, two SPI controllers, four I2C controllers,
three PCIe root complexes, GMAC, and the DMA controller.
The Shenzhen Rongda M0 and Milk-V Titan device trees add their
board-specific pin multiplexing, RTC devices, and Ethernet PHY
configuration. Both boards enable the three PCIe root complexes and
the GMAC described as disabled by default in the SoC DTS. The Titan
description also provides its GPIO wakeup keys.
The binding patches add the vendor, CPU, board, and peripheral compatible
strings consumed by the new device trees. The SPI, I2C, and AXI DMA nodes
use their respective generic DesignWare compatible strings as fallbacks.
An earlier version of the DP1000 SoC and board Devicetree support was
posted as part of a combined Devicetree and pinctrl series. The pinctrl
binding and driver were subsequently split out and merged separately.
This series carries the updated Devicetree portion.
Link: https://lore.kernel.org/all/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com/
This series depends on the UltraRISC DP1000 GMAC support series:
net: stmmac: Add common RGMII delay handling and DP1000 support
https://lore.kernel.org/netdev/20260907-dwmac-ultrarisc-v2-0-9a39bf8db313@ultrarisc.com/
Testing:
- Built dp1000-shenrongda-m0.dtb and dp1000-milkv-titan.dtb with
ARCH=riscv and W=1.
- Ran dt_binding_check for the modified bindings and the prerequisite
DP1000 GMAC binding.
- Validated both DTBs against the relevant Devicetree schemas with
CHECK_DTBS=y and the prerequisite GMAC series applied.
- Boot-tested both DTBs on Shenzhen Rongda M0 and Milk-V Titan. Verified
the CPU topology and CBO selftests, UART, SPI, I2C/RTC, system memory,
and all three PCIe root complexes. The expected PCIe endpoints were
enumerated on both boards.
- With the prerequisite GMAC series applied, ultrarisc-dwmac established
1000 Mb/s full-duplex links with the YT8531S PHY on M0 and the RTL8211F
PHY on Titan.
Signed-off-by: Jia Wang <wangjia at ultrarisc.com>
---
Changes in v2:
- Remove the dependency on the DP1000 clock series, which has since
been merged.
- Drop the generic DWMAC compatible patch; DP1000 GMAC support is handled
by a separate prerequisite series.
- Drop the RISC-V CPU binding yamllint fix, which has been applied.
- Add DP1000-specific resource constraints and hardware descriptions to
the SPI, I2C and DMA bindings.
- Correct the native chip-select count of SPI1 from three to four.
- Describe all eight per-channel DMA interrupts.
- Update the DP1000 GMAC nodes for the separate GMAC support series:
remove the generic DWMAC fallback, use "rgmii-id" for both boards, and
clarify the fixed MAC-side RGMII delays.
- Link to v1: https://patch.msgid.link/20260824-ultrarisc-dts-v1-0-61ab7aebe9e5@ultrarisc.com
To: Rob Herring <robh at kernel.org>
To: Krzysztof Kozlowski <krzk+dt at kernel.org>
To: Conor Dooley <conor+dt at kernel.org>
To: Paul Walmsley <pjw at kernel.org>
To: Palmer Dabbelt <palmer at dabbelt.com>
To: Albert Ou <aou at eecs.berkeley.edu>
To: Alexandre Ghiti <alex at ghiti.fr>
To: Jia Wang <wangjia at ultrarisc.com>
To: Daniel Lezcano <daniel.lezcano at kernel.org>
To: Thomas Gleixner <tglx at kernel.org>
To: Samuel Holland <samuel.holland at sifive.com>
To: Anup Patel <anup at brainfault.org>
To: Mark Brown <broonie at kernel.org>
To: Andi Shyti <andi.shyti at kernel.org>
To: Mika Westerberg <mika.westerberg at linux.intel.com>
To: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
To: Vinod Koul <vkoul at kernel.org>
To: Frank Li <Frank.Li at kernel.org>
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: Paul Walmsley <paul.walmsley at sifive.com>
Cc: Palmer Dabbelt <palmer at sifive.com>
Cc: Conor Dooley <conor at kernel.org>
Cc: linux-riscv at lists.infradead.org
Cc: linux-spi at vger.kernel.org
Cc: linux-i2c at vger.kernel.org
Cc: dmaengine at vger.kernel.org
---
Jia Wang (10):
dt-bindings: vendor-prefixes: Add shenrongda
dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible
dt-bindings: riscv: Add UltraRISC DP1000 board compatibles
dt-bindings: timer: Add UltraRISC DP1000 CLINT
spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC
dt-bindings: i2c: dw: Add compatible for UltraRISC DP1000 SoC
dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible
riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree
riscv: dts: ultrarisc: Add Milk-V Titan board device tree
.../devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 22 +
.../bindings/i2c/snps,designware-i2c.yaml | 15 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/ultrarisc.yaml | 27 +
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 16 +
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/ultrarisc/Makefile | 3 +
.../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi | 108 +++
.../boot/dts/ultrarisc/dp1000-milkv-titan.dts | 203 +++++
arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++
.../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++
.../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 113 +++
arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 899 +++++++++++++++++++++
16 files changed, 1561 insertions(+)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260522-ultrarisc-dts-9dab3a2316b6
prerequisite-message-id: <20260907-dwmac-ultrarisc-v2-0-9a39bf8db313 at ultrarisc.com>
prerequisite-patch-id: 92e6cf1352d54e283d7721dc1542b580b8a41be1
prerequisite-patch-id: 875c2058e9d8a983d785d7447374758f994dc847
prerequisite-patch-id: 060a9b129c32c623a52ab1ba66f7a357e54575ff
prerequisite-patch-id: 9aafbac6d2531a378b2057bf57787c814523f9d3
prerequisite-patch-id: d75120a112276bd966d37441bd4d631e1539d0e8
prerequisite-patch-id: ac933151b5a30d769d736be367b45dc6d1d9bfb5
Best regards,
--
Jia Wang <wangjia at ultrarisc.com>
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