[PATCH v1] riscv: skip software algning code for HAVE_EFFICIENT_UNALIGNED_ACCESS

[Paul Walmsley]

Hi,

On Tue, 1 Sep 2026, Andy Chiu wrote:

> We can jump straight into the copy loop if the kernel is compiled for a
> hardware that natively supports misaligned access. The user copy
> bandwidth improvement on K3 and Ascaolon is shown as below:
> 
> Misaligned user copy, size: 512B (offset: [0:15] except 0, 8)
> BW Improvement	| Write	| Read	|
> K3		| 6.19%	| 3.43%	|
> Ascalon		| 10.0%	| 11.4%	|
> 
> Aligned user copy, size: 512B (offset: 0, 8)
> BW Improvement	| Write	| Read	|
> K3		| 1.69%	| 0.90%	|
> Ascalon		| 1.25%	| 3.32%	|
> 
> Suggested-by: Anton Blanchard <antonb at tenstorrent.com>
> Signed-off-by: Andy Chiu <tchiu at tenstorrent.com>
> ---
>  arch/riscv/lib/uaccess.S | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
> index 4efea1b3326c..cf8586a937de 100644
> --- a/arch/riscv/lib/uaccess.S
> +++ b/arch/riscv/lib/uaccess.S
> @@ -76,6 +76,7 @@ SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled)
>  	li	a3, 9*SZREG-1 /* size must >= (word_copy stride + SZREG-1) */
>  	bltu	a2, a3, .Lbyte_copy_tail
>  
> +#if !defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)

[ ... ]

So I guess this is just targeting the fallback scalar path, and only for 
nonportable kernel builds?  Is it possible to use the result of dynamic 
misaligned access speed detection here, to improve performance for 
portable kernels as well?


- Paul