[PATCH v3 2/2] pwm: th1520: Fix 32-bit build with COMPILE_TEST
FUJITA Tomonori
tomo at flapping.org
Thu Oct 29 19:02:09 PDT 2026
From: FUJITA Tomonori <fujita.tomonori at gmail.com>
Fix the following build error on 32-bit ARM with COMPILE_TEST:
ERROR: modpost: drivers/pwm/pwm_th1520.ko: symbol '__aeabi_uldivmod' undefined!
The driver divides u64 values when it converts between nanoseconds and
clock cycles. On 32-bit ARM, these divisions are compiled to calls to
__aeabi_uldivmod, which the kernel does not provide.
Use div64_u64() and div64_u64_round_up() for these divisions, in the
same way as C drivers use div64_u64() and DIV64_U64_ROUND_UP(). The
results do not change.
Fixes: 3c180003dffb ("pwm: th1520: Fix missing Kconfig dependencies")
Reported-by: Andreas Hindborg <a.hindborg at kernel.org>
Closes: https://rust-for-linux.zulipchat.com/#narrow/channel/291565-Help/topic/64bit.20division.20in.20.60pwm_th1520.2Ers.60/near/626825599
Suggested-by: Uwe Kleine-König <ukleinek at kernel.org>
Assisted-by: LLM
Signed-off-by: FUJITA Tomonori <fujita.tomonori at gmail.com>
---
drivers/pwm/pwm_th1520.rs | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs
index 728993998446..bd05fe49650e 100644
--- a/drivers/pwm/pwm_th1520.rs
+++ b/drivers/pwm/pwm_th1520.rs
@@ -31,6 +31,10 @@
mem::DevresIoMem,
Io, //
},
+ math::{
+ div64_u64,
+ div64_u64_round_up, //
+ },
of,
platform,
prelude::*,
@@ -68,13 +72,13 @@ const fn th1520_pwm_fp(n: u32) -> usize {
fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 {
const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64;
- ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64
+ div64_u64(ns.saturating_mul(rate_hz), NSEC_PER_SEC_U64)
}
fn cycles_to_ns(cycles: u32, rate_hz: u64) -> u64 {
const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64;
- (u64::from(cycles) * NSEC_PER_SEC_U64).div_ceil(rate_hz)
+ div64_u64_round_up(u64::from(cycles) * NSEC_PER_SEC_U64, rate_hz)
}
/// Hardware-specific waveform representation for TH1520.
--
2.43.0
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