[PATCH v7 0/8] riscv: Introduce support for hardware break/watchpoints
Jesse Taube
jtaubepe at redhat.com
Tue Oct 27 12:56:43 PDT 2026
On Wed, Sep 30, 2026 at 2:39 AM Himanshu Chauhan
<himanshu.chauhan at oss.qualcomm.com> wrote:
>
> This patchset adds support for hardware breakpoints and watchpoints in the
> RISC-V architecture. The framework is built on top of the perf/ptrace subsystem
> and the SBI debug trigger extension (Sdtrig).
>
> Single stepping is ready with software support and mc6. Once, icount is fixed, the software
> supported single stepping will be put under a Kconfig option. Until then its default.
>
> Virtualization of debug triggers are pending. Patch set is ready but needs testing.
>
> Changes from v6:
> - Rebased to v7.3-rc5
> - Added HIT0/1 bit check/clear in breakpoint handler with EPC/Bp address check
> - Removed dbtr_shmem null check as pointed by Qinfang Deng
> - Fixed MEM_HI/MEM_LO macros to work both on rv64/32
> - Changed unsigned long to __u64 from hwdebug state struct and dropped packing
> - Gated HAVE_MIXED_BREAKPOINT_REGS with PERF_EVENTS
> - Software base single stepping with mcontrol6 trigger type.
> - icount is still under development.
> - Moved and and reworked instruction decoding code to a common file.
> - perf test suite now supported.
> - Breakpoint overflow signal handler
> - Breakpoint overflow sampling
> - Breakpoint accounting (needs sudo)
> - Watchpoint
> - Read Only Watchpoint
> - Write Only Watchpoint
> - Read / Write Watchpoint
> - Modify Watchpoint
> - __test_function in "Breakpoint overflow signal handler" is name noinline
> - Fixed warnings from checkpatch.pl --strict
>
> Changes from v5:
> - Rebased to v7.2-rc6
> - Simplified Macros in hw_breakpoint.h
> - Took care of the review comments
> - Added ptrace support for hardware break/watchpoints (new patch)
> - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH
> - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access
> - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool)
> - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up
> - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch)
>
> Changes from v4:
> - Rebased to v7.2-rc4
> - Fixed rv32 build error
> - Added pr_fmt to print KBUILD_MODNAME
> - Changed type of shmem_pa to phys_addr_t
> - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory
> - Print successful registration/unregistration message when no error
> - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer
> - Fixed warnings from checkpatch.pl --strict run
>
> Changes from v3:
> - Rebased to v7.1-rc3
> - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep
> STVAL-based matching as fallback
> - Improved watchpoint matching when STVAL reports the lowest accessed address
> for wider memory accesses
> - Program execute breakpoints with SIZE=0 (match any size) to avoid misses
> with 16-bit/compressed instruction addresses
> - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with
> sem_timedwait() timeout handling
> - Updated selftest breakpoint function so it cannot be inlined or optimized away
>
> Changes from v2:
> - Rebased to v7.0-rc1
> - Fixed warnings from checkpatch.pl --strict run
>
> Changes from v1:
> - The patch adding the SBI extension and function IDs is already merged; this
> series builds on top of that
> - Added breakpoint selftest in tools/testing/selftests/breakpoints/
>
> Specifications:
> ~~~~~~~~~~~~~~
> The SBI debug trigger extension is specified in Chapter 19 of the SBI
> specification:
> https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf
>
> The Sdtrig ISA is part of the RISC-V debug specification:
> https://github.com/riscv/riscv-debug-spec
>
> How to use:
> ~~~~~~~~~~~
> OpenSBI:
> https://github.com/riscv-software-src/opensbi.git
>
> QEMU:
> https://github.com/qemu/qemu.git
>
> Linux Kernel:
> Apply these patches on top of v7.3-rc5
>
> How to test:
> ~~~~~~~~~~~
> From the Linux kernel directory, first install the UAPI headers (required on a
> fresh tree so the compiler can locate <asm/ptrace.h> and the new
> NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES):
>
> make headers
>
> Then build the selftest:
>
> make -C tools/testing/selftests/breakpoints/
>
> This produces breakpoint_test_riscv under the same directory. Load it on the
> target and run. Sample output:
>
> # /apps/breakpoint_test_riscv
> # [perf_event]: Breakpoint test passed!
> # [perf_event]: Watchpoint test passed!
> # [ptrace]: Breakpoint test passed!
> # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2
> # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080
> # [ptrace]: Watchpoint test passed!
> # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0
> # [hbpregs]: Breakpoint test passed!
> # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0
> # [hbpregs]: Watchpoint test passed!
>
> Perf Test Suite:
> ~~~~~~~~~~~~~~~
> ~ # /apps/perf test -v 16 17 18 19
> 16: Breakpoint overflow signal handler : Ok
> 17: Breakpoint overflow sampling : Ok
> 18: Breakpoint accounting : Ok
> 19: Watchpoint :
> 19.1: Read Only Watchpoint : Ok
> 19.2: Write Only Watchpoint : Ok
> 19.3: Read / Write Watchpoint : Ok
> 19.4: Modify Watchpoint : Ok
>
> === Test Summary ===
> Passed main tests : 3
> Passed subtests : 4
> Skipped tests : 0
> Failed tests : 0
Thanks for these fixes! Sorry for the late reply.
If I dont review the next set within week send me an email to remind me.
It might also be a good idea to add icount like I did here
https://github.com/Mr-Bossman/linux/commit/eb0dbb8f87fe7e5df49d6f562ccff4097c41f362
Thanks,
Jesse Taube
> Himanshu Chauhan (8):
> riscv: Introduce support for hardware break/watchpoints
> riscv: Add breakpoint and watchpoint test for riscv
> riscv: ptrace support for hardware break/watchpoints
> selftests/breakpoints: extend riscv test for ptrace hw
> break/watchpoints
> RISC-V: Add fetch and decode helpers to a common file
> riscv: Add software supported single stepping with mc/mc6 triggers
> perf tests: add noinline to __test_function
> MAINTAINERS: Add entry for RISC-V Debugging
>
> MAINTAINERS | 11 +
> arch/riscv/Kconfig | 3 +
> arch/riscv/include/asm/hw_breakpoint.h | 331 +++++++
> arch/riscv/include/asm/insn.h | 15 +
> arch/riscv/include/asm/kdebug.h | 3 +-
> arch/riscv/include/asm/processor.h | 18 +
> arch/riscv/include/uapi/asm/ptrace.h | 50 +
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/hw_breakpoint.c | 879 ++++++++++++++++++
> arch/riscv/kernel/process.c | 5 +
> arch/riscv/kernel/ptrace.c | 507 ++++++++++
> arch/riscv/kernel/traps.c | 6 +
> arch/riscv/kernel/traps_misaligned.c | 52 +-
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/insn.c | 263 ++++++
> include/uapi/linux/elf.h | 4 +
> tools/include/uapi/linux/elf.h | 2 +
> tools/perf/tests/bp_signal.c | 2 +-
> tools/testing/selftests/breakpoints/Makefile | 5 +
> .../breakpoints/breakpoint_test_riscv.c | 769 +++++++++++++++
> 20 files changed, 2874 insertions(+), 53 deletions(-)
> create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
> create mode 100644 arch/riscv/kernel/hw_breakpoint.c
> create mode 100644 arch/riscv/lib/insn.c
> create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
>
> --
> 2.43.0
>
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