[PATCH v3 0/2] riscv: support CPUs with Zalrsc but not Zaamo

[Vladimir Kondratiev]

On 10/26/26 12:30, Peter Zijlstra wrote:
> The comment with RISCV_QUEUED_SPINLOCKS state that Zalrsc requires that
> cmpxchg() loops have forward progress; which is much stronger than the
> typical LL/SC implementation.
> 
> Does this MIPS thing indeed provide this?

You mean Ziccrse extension? Yes, p8700 does provide it. I explicitly
confirmed it with hardware designers.

In fact, I use RISCV_QUEUED_SPINLOCKS on this platform

Thanks, Vladimir